lab5 report
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2020301918-李懋良-试点班第5个报告.docx
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2020301918-李懋良-试点班第5个报告.docx
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12
kern/main.c
12
kern/main.c
@ -41,7 +41,6 @@ init_segment_regs(PROCESS *p_proc)
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static inline void
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lml_map(phyaddr_t cr3, uintptr_t vaddr, phyaddr_t paddr, u32 flags) {
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uintptr_t *pde_ptr = (uintptr_t *)K_PHY2LIN(cr3);
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// pde_ptr += PDX(3 * GB); // get page table base addr
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// get pdx item, pde_ptr + PDX(vaddr)
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pde_ptr += PDX(vaddr);
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if (!(*pde_ptr & PTE_P)) {
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@ -100,7 +99,8 @@ void kernel_main(void)
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if (phdr->p_type == PT_LOAD) {
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u32 vpage_fst = phdr->p_va & (~0xfff); // clear low 12 bit, start of the first pg
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u32 vpage_lst = (phdr->p_va + phdr->p_memsz - 1) & (~0xfff); // start of the last pg
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// in fact, we allocate 4k aligned vpage to every segment; its ok because elf32 segment align is 0x1000
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// in fact, we allocate 4k aligned vpage to every segment;
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// its ok because elf32 segment align is 0x1000
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u32 page_num = ((vpage_lst - vpage_fst) >> 12) + 1;
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phyaddr_t newpage = 0; // useless initialization
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for (int j = 0; j < page_num; ++ j) {
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@ -123,12 +123,8 @@ void kernel_main(void)
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for (int i = 0; i < 8; ++ i) {
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lml_map(p_proc->pcb.cr3, (3*GB - (8-i)*PGSIZE), ustack_low + i*PGSIZE, PTE_P | PTE_W | PTE_U);
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}
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p_proc->pcb.user_regs.esp = 3*GB;
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// p_proc->pcb.user_regs.esp -= 4;
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// uintptr_t* ustack_top = (uintptr_t*)K_PHY2LIN(ustack_high + PGSIZE);
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// ustack_top --;
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// *ustack_top = ehdr->e_entry;
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p_proc->pcb.user_regs.eip = ehdr->e_entry;
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p_proc->pcb.user_regs.esp = 3*GB; // high to low stack
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p_proc->pcb.user_regs.eip = ehdr->e_entry; // refer to restart:
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// 初始化用户寄存器
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p_proc->pcb.user_regs.eflags = 0x1202; /* IF=1, IOPL=1 */
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