From 47053d35da80f37544a7e0ac77068eb8fa2d0020 Mon Sep 17 00:00:00 2001 From: ridethepig Date: Thu, 4 May 2023 10:54:25 +0800 Subject: [PATCH] quite a lot update --- ...rganization_and_Design_1681729306797_0.edn | 2406 ++++++++++++++++- ...cy_Comes_for_Free_with_1682647018871_0.edn | 464 +++- journals/2023_04_30.md | 1 + journals/2023_05_01.md | 4 + journals/2023_05_02.md | 3 + journals/2023_05_03.md | 4 + ...Organization_and_Design_1681729306797_0.md | 542 +++- ...ncy_Comes_for_Free_with_1682647018871_0.md | 113 +- pages/hls__ostep_1681115599584_0.md | 1 + 9 files changed, 3524 insertions(+), 14 deletions(-) create mode 100644 journals/2023_05_01.md create mode 100644 journals/2023_05_02.md create mode 100644 journals/2023_05_03.md diff --git a/assets/Computer_Organization_and_Design_1681729306797_0.edn b/assets/Computer_Organization_and_Design_1681729306797_0.edn index 47917a9..0daeb49 100644 --- a/assets/Computer_Organization_and_Design_1681729306797_0.edn +++ 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:content {:text "Transitions from state 1 to state 2 are caused by failures, and transitions from state2 to state 1 are called restorations."}, + :properties {:color "yellow"}} + {:id #uuid "644f4535-12cc-4669-bdbe-4d72b5066fae", + :page 497, + :position {:bounding {:x1 475.21478271484375, + :y1 682.0625, + :x2 777.3880004882812, + :y2 699.0625, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 475.21478271484375, + :y1 682.0625, + :x2 777.3880004882812, + :y2 699.0625, + :width 895, + :height 1103.8335266977099}), + :page 497}, + :content {:text " Failures can be permanent or intermittent."}, + :properties {:color "yellow"}} + {:id #uuid "644f456f-e4bb-44be-8352-ad557cd80060", + :page 497, + :position {:bounding {:x1 256.875, + :y1 761.625, + :x2 691.90673828125, + :y2 779.03125, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 256.875, + :y1 761.625, + :x2 691.90673828125, + :y2 779.03125, + :width 895, + :height 1103.8335266977099}), + :page 497}, + :content {:text "Reliability is a measure of the continuous service accomplishment—"}, + :properties {:color "yellow"}} + {:id #uuid "644f4583-1a89-4136-b6e8-ae34cd452815", + :page 497, + :position {:bounding {:x1 603.03125, + :y1 781.515625, + :x2 805.4700927734375, + :y2 798.921875, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 603.03125, + :y1 781.515625, + :x2 805.4700927734375, + :y2 798.921875, + :width 895, + :height 1103.8335266977099}), + :page 497}, + :content {:text " mean time to failure (MTTF)"}, + :properties {:color "yellow"}} + {:id #uuid "644f458b-0d1e-4799-be33-b9251e95d4fe", + :page 497, + :position {:bounding {:x1 515.15625, + :y1 801.40625, + :x2 683.6367797851562, + :y2 818.8125, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 515.15625, + :y1 801.40625, + :x2 683.6367797851562, + :y2 818.8125, + :width 895, + :height 1103.8335266977099}), + :page 497}, + :content {:text "annual failure rate (AFR),"}, + :properties {:color "yellow"}} + {:id #uuid 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Av"}, + :properties {:color "yellow"}} + {:id #uuid "644f4720-89b2-4fd5-813f-1a9f18579745", + :page 498, + :position {:bounding {:x1 499.9492492675781, + :y1 776.53125, + :x2 629.5648193359375, + :y2 793.53125, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 499.9492492675781, + :y1 776.53125, + :x2 629.5648193359375, + :y2 793.53125, + :width 895, + :height 1103.8335266977099}), + :page 498}, + :content {:text "ys to improve MTTF"}, + :properties {:color "yellow"}} + {:id #uuid "644f47cb-b392-4558-a654-ce01bcf35209", + :page 499, + :position {:bounding {:x1 0, + :y1 78.96875, + :x2 805.533447265625, + :y2 280.75, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 0, + :y1 78.96875, + :x2 0, + :y2 102.96875, + :width 895, + :height 1103.8335266977099} + {:x1 0, + :y1 95.5625, + :x2 0, + :y2 119.5625, + :width 895, + :height 1103.8335266977099} + {:x1 737.203125, + :y1 223.96875, + :x2 805.533447265625, + :y2 240.96875, + :width 895, + :height 1103.8335266977099} + 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lower than the probability of having two, s"}, + :properties {:color "yellow"}} + {:id #uuid "644f49ab-9ec8-46f0-9dcb-86eb1da64df2", + :page 499, + :position {:bounding {:x1 353.921875, + :y1 989.703125, + :x2 621.8609619140625, + :y2 1006.703125, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 353.921875, + :y1 989.703125, + :x2 621.8609619140625, + :y2 1006.703125, + :width 895, + :height 1103.8335266977099}), + :page 499}, + :content {:text "Hamming Error Correction Code (ECC) "}, + :properties {:color "yellow"}} + {:id #uuid "644f4c11-76c4-4c50-8278-f5a18415cad6", + :page 501, + :position {:bounding {:x1 681.3995361328125, + :y1 609.953125, + :x2 714.12548828125, + :y2 626.953125, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 681.3995361328125, + :y1 609.953125, + :x2 714.12548828125, + :y2 626.953125, + :width 895, + :height 1103.8335266977099}), + :page 501}, + :content {:text "Voila"}, + :properties {:color "green"}} + {:id #uuid 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processor-bound programs have zero virtualization overhead"}, + :properties {:color "yellow"}} + {:id #uuid "644f52a8-98fb-466b-92cf-7c0f942382b2", + :page 504, + :position {:bounding {:x1 0, + :y1 477.21875, + :x2 657.763916015625, + :y2 914.5625, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 0, + :y1 477.21875, + :x2 0, + :y2 501.21875, + :width 895, + :height 1103.8335266977099} + {:x1 0, + :y1 493.8125, + :x2 0, + :y2 517.8125, + :width 895, + :height 1103.8335266977099} + {:x1 484.4814453125, + :y1 857.78125, + :x2 657.7326049804688, + :y2 874.78125, + :width 895, + :height 1103.8335266977099} + {:x1 89.46875, + :y1 877.671875, + :x2 657.763916015625, + :y2 895.078125, + :width 895, + :height 1103.8335266977099} + {:x1 89.46875, + :y1 897.5625, + :x2 500.3424377441406, + :y2 914.5625, + :width 895, + :height 1103.8335266977099}), + :page 504}, + :content {:text ". I/O-intensive workloads are generally also OS-intensive, executing many system calls and privileged instructions that can result in high virtualization overhead"}, + :properties {:color "yellow"}} + {:id #uuid "644f52db-8deb-4e8b-8a11-e59b2bbfbe26", + :page 505, + :position {:bounding {:x1 237, + :y1 191.625, + :x2 651.793212890625, + :y2 217.625, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 237, + :y1 191.625, + :x2 651.793212890625, + :y2 217.625, + :width 895, + :height 1103.8335266977099}), + :page 505}, + :content {:text "Requirements of a Virtual Machine Monitor"}, + :properties {:color "yellow"}} + {:id #uuid "644f533e-a31c-4916-bb47-2c97eae78310", + :page 505, + :position {:bounding {:x1 0, + :y1 112.15625, + :x2 805.3128051757812, + :y2 331.125, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 0, + :y1 112.15625, + :x2 0, + :y2 136.15625, + :width 895, + :height 1103.8335266977099} + {:x1 276.78125, + :y1 294.234375, + :x2 805.3128051757812, + :y2 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directly."}, + :properties {:color "yellow"}} + {:id #uuid "644f5381-dd30-4674-b37e-ce080e71a4a2", + :page 505, + :position {:bounding {:x1 237.015625, + :y1 977.109375, + :x2 302.90594482421875, + :y2 994.109375, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 237.015625, + :y1 977.109375, + :x2 302.90594482421875, + :y2 994.109375, + :width 895, + :height 1103.8335266977099}), + :page 505}, + :content {:text "culprits "}, + :properties {:color "green"}} + {:id #uuid "644f5401-cfe8-439b-af2e-d91bc6dae442", + :page 505, + :position {:bounding {:x1 276.78125, + :y1 662.1875, + :x2 601.4721069335938, + :y2 679.1875, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 276.78125, + :y1 662.1875, + :x2 601.4721069335938, + :y2 679.1875, + :width 895, + :height 1103.8335266977099}), + :page 505}, + :content {:text "At least two processor modes, system and user."}, + :properties {:color "yellow"}} + {:id #uuid "644f5403-7aab-4e4e-ae71-87aa2d22bbbd", + :page 505, + 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"644f5b71-6ca0-47f3-8a20-9cc15c1fa0e0", + :page 515, + :position {:bounding {:x1 491.40692138671875, + :y1 593.421875, + :x2 535.9385375976562, + :y2 613.421875, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 491.40692138671875, + :y1 593.421875, + :x2 535.9385375976562, + :y2 613.421875, + :width 895, + :height 1103.8335266977099}), + :page 515}, + :content {:text "duality"}, + :properties {:color "green"}} + {:id #uuid "644f5d06-3450-4d12-96e5-374712790d9e", + :page 517, + :position {:bounding {:x1 237, + :y1 127.96875, + :x2 629.7202758789062, + :y2 153.96875, + :width 895, + :height 1103.8335266977099}, + :rects ({:x1 237, + :y1 127.96875, + :x2 629.7202758789062, + :y2 153.96875, + :width 895, + :height 1103.8335266977099}), + :page 517}, + :content {:text "Making Address Translation Fast: the TLB"}, + :properties {:color "yellow"}} + {:id #uuid "644f5d6e-0c4e-48ad-9284-7b6247cc3d15", + :page 517, + :position {:bounding {:x1 0, + :y1 244.90625, + :x2 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When a TLB miss occurs, the MIPS hardware saves the page number of the reference in a special register and generates an exception. "}, + :properties {:color "yellow"}} + {:id #uuid "644f6250-82e1-4286-b25a-e4f4eb0eb622", + :page 519, + :position {:bounding {:x1 0, + :y1 294.6875, + :x2 907.3255615234375, + :y2 574.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 294.6875, + :x2 0, + :y2 318.6875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.90625, + :y1 532.453125, + :x2 907.3255615234375, + :y2 552.453125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.90625, + :y1 554.859375, + :x2 809.8880004882812, + :y2 574.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 519}, + :content {:text "Using a special set of system instructions that can update the TLB, the operating system places the physical address from the page table into the TLB"}, + :properties {:color "yellow"}} + {:id #uuid "644f62a6-7b6d-4434-bc3d-233892af468f", + :page 519, + :position {:bounding {:x1 0, + :y1 361.0625, + :x2 907.4433288574219, + :y2 664.46875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 361.0625, + :x2 0, + :y2 385.0625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 373.6523132324219, + :y1 622.0625, + :x2 907.4433288574219, + :y2 642.0625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.90625, + :y1 644.46875, + :x2 394.92498779296875, + :y2 664.46875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 519}, + :content {:text "A true page fault occurs if the page table entry does not have a valid physical address"}, + :properties {:color "yellow"}} + {:id #uuid "644f62bd-6a29-40bc-a634-15fed6bc1ec9", + :page 519, + :position {:bounding {:x1 0, + :y1 377.65625, + :x2 906.948974609375, + :y2 686.875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 377.65625, + :x2 0, + :y2 401.65625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 402.91021728515625, + :y1 644.46875, + :x2 906.948974609375, + :y2 664.46875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.90625, + :y1 666.875, + :x2 747.1682739257812, + :y2 686.875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 519}, + :content {:text " The hardware maintains an index that indicates the recommended entry to replace; the recommended entry is chosen randomly."}, + :properties {:color "yellow"}} + {:id #uuid "644f6370-8fd9-4a5e-92e3-09b74f6baa04", + :page 522, + :position {:bounding {:x1 0, + :y1 145.34375, + :x2 741.0742797851562, + :y2 539.15625, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 145.34375, + :x2 0, + :y2 169.34375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 424.4248352050781, + :y1 496.625, + :x2 741.0742797851562, + :y2 518.625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 100.796875, + :y1 517.15625, + :x2 477.369384765625, + :y2 539.15625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 522}, + :content {:text "all memory addresses are translated to physical addresses before the cache is accessed"}, + :properties {:color "yellow"}} + {:id #uuid "644f6397-14d2-491c-9cef-bbfd6e5cca8f", + :page 522, + :position {:bounding {:x1 370.203125, + :y1 642.1875, + :x2 567.4990844726562, + :y2 664.1875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 370.203125, + :y1 642.1875, + :x2 567.4990844726562, + :y2 664.1875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 522}, + :content {:text "virtually addressed cache"}, + :properties {:color "yellow"}} + {:id #uuid "644f6434-eb87-405e-9190-4f67466af467", + :page 523, + :position {:bounding {:x1 0, + :y1 45.78125, + :x2 907.22119140625, + :y2 229.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 45.78125, + :x2 0, + :y2 69.78125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 367.328125, + :y1 187.328125, + :x2 907.22119140625, + :y2 209.328125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 425.453125, + :y1 190.328125, + :x2 907.22119140625, + :y2 207.125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 207.859375, + :x2 597.1638793945312, + :y2 229.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 523}, + :content {:text "aliasing. Aliasing occurs when the same object has two names—in this case, two virtual addresses for the same page."}, + :properties {:color "yellow"}} + {:id #uuid "644f6491-3e52-4db7-a824-5988e124ee1c", + :page 523, + :position {:bounding {:x1 0, + :y1 178.53125, + :x2 907.1993408203125, + :y2 394.109375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 178.53125, + :x2 0, + :y2 202.53125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 304.64227294921875, + :y1 351.578125, + :x2 907.1993408203125, + :y2 373.578125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.921875, + :y1 372.109375, + :x2 326.41583251953125, + :y2 394.109375, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 523}, + :content {:text "common compromise between these two design points is caches that are virtually indexed"}, + :properties {:color "yellow"}} + {:id #uuid "644f65b8-c079-42ce-a6b6-e1c56dbf45e9", + :page 525, + :position {:bounding {:x1 266.921875, + :y1 625.546875, + :x2 665.9844360351562, + :y2 655.546875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 266.921875, + :y1 625.546875, + :x2 665.9844360351562, + :y2 655.546875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 525}, + :content {:text "Handling TLB Misses and Page Faults"}, + :properties {:color "yellow"}} + {:id #uuid "644f65cf-03a5-4132-b091-e08b9ce9002a", + :page 523, + :position {:bounding {:x1 266.921875, + :y1 560.796875, + :x2 761.182861328125, + :y2 590.796875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 266.921875, + :y1 560.796875, + :x2 761.182861328125, + :y2 590.796875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 523}, + :content {:text "Implementing Protection with Virtual Memory"}, + :properties {:color "yellow"}} + {:id #uuid "644f65f9-38a8-4ead-90f5-494c0b2e3191", + :page 523, + :position {:bounding {:x1 0, + :y1 593.375, + :x2 907.5158081054688, + :y2 1075.65625, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 593.375, + :x2 0, + :y2 617.375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.296875, + :y1 1033.25, + :x2 907.5158081054688, + :y2 1053.25, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.328125, + :y1 1055.65625, + :x2 365.8406066894531, + :y2 1075.65625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 523}, + :content {:text "Provide a portion of the processor state that a user process can read but not write."}, + :properties {:color "yellow"}} + {:id #uuid "644f660f-7534-4124-9b7e-32cd2ce2c77a", + :page 524, + :position {:bounding {:x1 0, + :y1 45.78125, + :x2 741.2855224609375, + :y2 245.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 45.78125, + :x2 0, + :y2 69.78125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 151.15625, + :y1 203.453125, + :x2 741.2855224609375, + :y2 223.453125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 151.1875, + :y1 225.859375, + :x2 400.7629089355469, + :y2 245.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 524}, + :content {:text "Provide mechanisms whereby the processor can go from user mode to supervisor mode and vice versa. T"}, + :properties {:color "yellow"}} + {:id #uuid "644f67c6-de09-4546-b3a6-cbb286cca5bb", + :page 525, + :position {:bounding {:x1 491.1572570800781, + :y1 728.421875, + :x2 864.9146728515625, + :y2 748.421875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 491.1572570800781, + :y1 728.421875, + :x2 864.9146728515625, + :y2 748.421875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 525}, + :content {:text " a TLB miss can indicate one of two possibilities:"}, + :properties {:color "yellow"}} + {:id #uuid "644f6897-2635-4cb9-ae6b-2515dc05694b", + :page 525, + :position {:bounding {:x1 0, + :y1 527, + :x2 907.3702392578125, + :y2 938.8125, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 527, + :x2 0, + :y2 551, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 0, + :y1 543.59375, + :x2 0, + :y2 567.59375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 289.328125, + :y1 874, + :x2 907.208251953125, + :y2 894, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 896.40625, + :x2 907.3702392578125, + :y2 916.40625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 918.8125, + :x2 575.9363403320312, + :y2 938.8125, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 525}, + :content {:text "MIPS traditionally handles a TLB miss in software. It brings in the page table entry from memory and then re-executes the instruction that caused the TLB miss. Upon re-executing, it will get a TLB hit. "}, + :properties {:color "yellow"}} + {:id #uuid "644f68df-1f9b-4430-a2ea-09ee1ca7361f", + :page 526, + :position {:bounding {:x1 0, + :y1 145.34375, + :x2 741.370361328125, + :y2 369.078125, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 145.34375, + :x2 0, + :y2 169.34375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 499.1952209472656, + :y1 326.671875, + :x2 741.370361328125, + :y2 346.671875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 100.796875, + :y1 349.078125, + :x2 581.2405395507812, + :y2 369.078125, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 526}, + :content {:text " We must prevent the write into memory from actually completing when there is a page fault; "}, + :properties {:color "yellow"}} + {:id #uuid "644f6974-151b-46fa-afe2-ceed4ec48722", + :page 527, + :position {:bounding {:x1 0, + :y1 377.65625, + :x2 907.0743408203125, + :y2 1067.203125, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 377.65625, + :x2 0, + :y2 401.65625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 0, + :y1 394.25, + :x2 0, + :y2 418.25, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 553.9938354492188, + :y1 1002.40625, + :x2 906.9071044921875, + :y2 1022.40625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.921875, + :y1 1024.796875, + :x2 907.0743408203125, + :y2 1044.796875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.921875, + :y1 1047.203125, + :x2 448.5799255371094, + :y2 1067.203125, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 527}, + :content {:text "S. When a TLB miss occurs, the MIPS hardware saves the page number of the reference in a special register called BadVAddr and generates an exception."}, + :properties {:color "yellow"}} + {:id #uuid "644f69a6-31f7-4f57-8c78-75a19f0d83fd", + :page 528, + :position {:bounding {:x1 0, + :y1 29.1875, + :x2 745.125, + :y2 195.46875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 29.1875, + :x2 0, + :y2 53.1875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 100.796875, + :y1 169.859375, + :x2 430.2232971191406, + :y2 189.859375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 446.515625, + :y1 169.859375, + :x2 745.125, + :y2 189.859375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 430.21875, + :y1 183.46875, + :x2 446.5349426269531, + :y2 195.46875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 528}, + :content {:text "Control is transferred to address 8000 0000 hex, the location of the TLB miss handler."}, + :properties {:color "yellow"}} + {:id #uuid "644f69dd-753d-4df6-b0fc-4f112a12f0ce", + :page 528, + :position {:bounding {:x1 0, + :y1 112.15625, + :x2 741.0813598632812, + :y2 301.875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 112.15625, + :x2 0, + :y2 136.15625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 211.48458862304688, + :y1 259.46875, + :x2 741.0813598632812, + :y2 279.46875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 100.796875, + :y1 281.875, + :x2 162.4828338623047, + :y2 301.875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 528}, + :content {:text " MIPS hardware places everything you need in the special Context register"}, + :properties {:color "yellow"}} + {:id #uuid "644f6cf2-142f-4b34-a4c1-06de2a87879a", + :page 530, + :position {:bounding {:x1 100.796875, + :y1 966.6875, + :x2 595.5134887695312, + :y2 986.6875, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 100.796875, + :y1 966.6875, + :x2 191.0458221435547, + :y2 986.6875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 208.203125, + :y1 966.6875, + :x2 595.5134887695312, + :y2 986.6875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 188.59375, + :y1 969.6875, + :x2 191.0458221435547, + :y2 984.625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 530}, + :content {:text "FIGURE 5.34 MIPS code to save and restore state on an exception."}, + :properties {:color "yellow"}} + {:id #uuid "644f6d39-ad59-4a15-81a9-8dede8bef344", + :page 529, + :position {:bounding {:x1 0, + :y1 161.9375, + :x2 907.2249145507812, + :y2 445.390625, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 161.9375, + :x2 0, + :y2 185.9375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 0, + :y1 178.53125, + :x2 0, + :y2 202.53125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 889.2879028320312, + :y1 382.328125, + :x2 907.2086181640625, + :y2 404.328125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 402.859375, + :x2 907.2249145507812, + :y2 424.859375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 405.859375, + :x2 907.2249145507812, + :y2 422.65625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 423.390625, + :x2 877.2501831054688, + :y2 445.390625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 426.390625, + :x2 868.0960693359375, + :y2 443.1875, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 529}, + :content {:text "To avoid the problem of a page fault during this low-level exception code, MIPS sets aside a portion of its address space that cannot have page faults, called unmapped. "}, + :properties {:color "yellow"}} + {:id #uuid "644f6d8d-7c2f-4cb7-b689-eb282d35f411", + :page 529, + :position {:bounding {:x1 0, + :y1 510.40625, + :x2 907.2192993164062, + :y2 956.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 510.40625, + :x2 0, + :y2 534.40625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 889.5509033203125, + :y1 914.328125, + :x2 907.2192993164062, + :y2 936.328125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 934.859375, + :x2 538.9133911132812, + :y2 956.859375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 266.9375, + :y1 937.859375, + :x2 538.3015747070312, + :y2 954.65625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 529}, + :content {:text "he VMM maintains a shadow page table "}, + :properties {:color "yellow"}} + {:id #uuid "644f6e31-ed3f-4bbf-8f30-53fe28e9e518", + :page 534, + :position {:bounding {:x1 100.796875, + :y1 144.640625, + :x2 562.2498779296875, + :y2 174.640625, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 100.796875, + :y1 144.640625, + :x2 562.2498779296875, + :y2 174.640625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 534}, + :content {:text "Question 1: Where Can a Block Be Placed?"}, + :properties {:color "yellow"}} + {:id #uuid "644f6e76-bf1e-4def-b9c0-75f1faf3b5c6", + :page 534, + :position {:bounding {:x1 0, + :y1 45.78125, + :x2 741.2048950195312, + :y2 267.515625, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 45.78125, + :x2 0, + :y2 69.78125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 0, + :y1 62.375, + :x2 0, + :y2 86.375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 633.9576416015625, + :y1 202.703125, + :x2 740.6068115234375, + :y2 222.703125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 100.796875, + :y1 225.109375, + :x2 741.2048950195312, + :y2 245.109375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 100.796875, + :y1 247.515625, + :x2 658.7503051757812, + :y2 267.515625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 534}, + :content {:text ". As mentioned above, this entire range of schemes can be thought of as variations on a set-associative scheme where the number of sets and the number of blocks per set varies"}, + :properties {:color "yellow"}} + {:id #uuid "644f6ec3-e710-4abf-94a2-9f0c362e40e8", + :page 535, + :position {:bounding {:x1 266.921875, + :y1 261.125, + :x2 640.56201171875, + :y2 291.125, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 266.921875, + :y1 261.125, + :x2 640.56201171875, + :y2 291.125, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 535}, + :content {:text "Question 2: How Is a Block Found?"}, + :properties {:color "yellow"}} + {:id #uuid "644f6f0b-c5e3-4c38-90ec-67e3118b5c3d", + :page 536, + :position {:bounding {:x1 0, + :y1 62.375, + :x2 619.14111328125, + :y2 294.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 62.375, + :x2 0, + :y2 86.375, + :width 1007.9990666666666, + :height 1243.1990666666666} + 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A memory system is coherent if"}, + :properties {:color "yellow"}} + {:id #uuid "644f77b5-83a5-4fb1-b3a6-3a2db489da39", + :page 545, + :position {:bounding {:x1 0, + :y1 493.8125, + :x2 907.5958251953125, + :y2 985.09375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 493.8125, + :x2 0, + :y2 517.8125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 0, + :y1 510.40625, + :x2 0, + :y2 534.40625, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.328125, + :y1 920.296875, + :x2 907.4578247070312, + :y2 940.296875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.34375, + :y1 942.703125, + :x2 907.5958251953125, + :y2 962.703125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.34375, + :y1 965.09375, + :x2 663.4116821289062, + :y2 985.09375, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 545}, + :content {:text "A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P."}, + :properties {:color "yellow"}} + {:id #uuid "644f77c2-e346-4ffc-bb20-a1b3933fe9fc", + :page 545, + :position {:bounding {:x1 0, + :y1 560.1875, + :x2 907.429443359375, + :y2 1085.90625, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 560.1875, + :x2 0, + :y2 584.1875, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 0, + :y1 576.78125, + :x2 0, + :y2 600.78125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.34375, + :y1 1021.09375, + :x2 907.429443359375, + :y2 1041.09375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.34375, + :y1 1043.5, + :x2 907.169677734375, + :y2 1063.5, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 317.34375, + :y1 1065.90625, + :x2 842.5884399414062, + :y2 1085.90625, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 545}, + :content {:text "A read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses. 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data item can be moved to a local cache and used there in a transparent fashion."}, + :properties {:color "yellow"}} + {:id #uuid "644f78b7-c9fa-4854-824d-a8d0952ad3be", + :page 547, + :position {:bounding {:x1 0, + :y1 12.59375, + :x2 907.3712158203125, + :y2 189.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}, + :rects ({:x1 0, + :y1 12.59375, + :x2 0, + :y2 36.59375, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 311.71875, + :y1 147.453125, + :x2 907.3712158203125, + :y2 167.453125, + :width 1007.9990666666666, + :height 1243.1990666666666} + {:x1 311.71875, + :y1 169.859375, + :x2 703.0508422851562, + :y2 189.859375, + :width 1007.9990666666666, + :height 1243.1990666666666}), + :page 547}, + :content {:text "Replication: When shared data are being simultaneously read, the caches make a copy of the data item in the local cache."}, + :properties {:color "yellow"}} + {:id #uuid "644f7956-11ad-4140-b966-6d2061ae6fb2", + :page 547, + :position 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allow multiple, independent, parallel accesses, provided the accesses are to different banks."}, + :properties {:color "yellow"}} + {:id #uuid "644faeff-a7cf-4a48-b257-50e090ca62be", + :page 558, + :position {:bounding {:x1 454.953125, + :y1 1033.34375, + :x2 621.8716430664062, + :y2 1054.34375, + :width 1079.999, + :height 1331.999}, + :rects ({:x1 454.953125, + :y1 1033.34375, + :x2 621.8716430664062, + :y2 1054.34375, + :width 1079.999, + :height 1331.999}), + :page 558}, + :content {:text "nonblocking cache"}, + :properties {:color "yellow"}} + {:id #uuid "644faf31-abe7-4938-b43a-15ca77c5a20a", + :page 559, + :position {:bounding {:x1 278.2077331542969, + :y1 207.0625, + :x2 622.2258911132812, + :y2 228.0625, + :width 1079.999, + :height 1331.999}, + :rects ({:x1 278.2077331542969, + :y1 207.0625, + :x2 622.2258911132812, + :y2 228.0625, + :width 1079.999, + :height 1331.999}), + :page 559}, + :content {:text " prefetch mechanism for data accesses. I"}, + :properties {:color "yellow"}} + {:id #uuid "644fafd9-52b6-4378-b808-35d07dd67108", + :page 561, + :position {:bounding {:x1 408.576416015625, + :y1 1054.875, + :x2 455.5439147949219, + :y2 1075.875, + :width 1079.999, + :height 1331.999}, + :rects ({:x1 408.576416015625, + :y1 1054.875, + :x2 455.5439147949219, + :y2 1075.875, + :width 1079.999, + :height 1331.999}), + :page 561}, + :content {:text "saga "}, + :properties {:color "green"}} + {:id #uuid "644fb0c3-4e0b-41ea-8edb-01e11b936c65", + :page 568, + :position {:bounding {:x1 313.4110412597656, + :y1 531.0625, + :x2 423.11773681640625, + :y2 552.0625, + :width 1079.999, + :height 1331.999}, + :rects ({:x1 313.4110412597656, + :y1 531.0625, + :x2 423.11773681640625, + :y2 552.0625, + :width 1079.999, + :height 1331.999}), + :page 568}, + :content {:text "underscored "}, + :properties {:color "green"}} + {:id #uuid "644fb0df-1bf0-479c-bb16-de1b6729faa4", + :page 565, + :position {:bounding {:x1 0, + :y1 62.375, + :x2 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:x2 1134.9884033203125, + :y2 1175.015625, + :width 1387.2, + :height 1795.2}), + :page 2}, + :content {:text "modern storage devices"}, + :properties {:color "yellow"}} + {:id #uuid "64511979-cee9-4f46-87ba-6bbfe86bf0a4", + :page 2, + :position {:bounding {:x1 0, + :y1 1290.3125, + :x2 1264.7996826171875, + :y2 1585.734375, + :width 1387.2, + :height 1795.2}, + :rects ({:x1 0, + :y1 1290.3125, + :x2 0, + :y2 1314.3125, + :width 1387.2, + :height 1795.2} + {:x1 743.109375, + :y1 1528.625, + :x2 1264.7996826171875, + :y2 1558.625, + :width 1387.2, + :height 1795.2} + {:x1 719.703125, + :y1 1555.734375, + :x2 780.1452026367188, + :y2 1585.734375, + :width 1387.2, + :height 1795.2}), + :page 2}, + :content {:text "Previous approaches are limited to atomicity unit of CPU writes."}, + :properties {:color "yellow"}} + {:id #uuid "64511f4c-4338-41ad-9264-263ed5a08bf4", + :page 3, + :position {:bounding {:x1 0, + :y1 278.09375, + :x2 670.4557495117188, + :y2 754.328125, + :width 1387.2, + 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guarantee the persistence of memory writes once they become globally visible, "}, + :properties {:color "yellow"}} + {:id #uuid "6451205e-7f48-43e8-8704-d221d806cc18", + :page 3, + :position {:bounding {:x1 0, + :y1 427.4375, + :x2 627.459716796875, + :y2 940.53125, + :width 1305.6, + :height 1689.6}, + :rects ({:x1 0, + :y1 427.4375, + :x2 0, + :y2 451.4375, + :width 1305.6, + :height 1689.6} + {:x1 474.9247131347656, + :y1 887.015625, + :x2 627.459716796875, + :y2 915.015625, + :width 1305.6, + :height 1689.6} + {:x1 115.1875, + :y1 912.53125, + :x2 263.9544982910156, + :y2 940.53125, + :width 1305.6, + :height 1689.6}), + :page 3}, + :content {:text "everal challenges prevent RTM-PM "}, + :properties {:color "yellow"}} + {:id #uuid "64512109-8ab0-49aa-b6a3-1524df0631ef", + :page 3, + :position {:bounding {:x1 261.0550537109375, + :y1 1498.546875, + :x2 544.9708251953125, + :y2 1520.546875, + :width 1305.6, + :height 1689.6}, + :rects ({:x1 261.0550537109375, + :y1 1498.546875, + :x2 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"}, + :properties {:color "yellow"}} + {:id #uuid "64527149-e50e-46c8-990f-0465060f9a5a", + :page 4, + :position {:bounding {:x1 762.90625, + :y1 904.640625, + :x2 920.9835815429688, + :y2 935.640625, + :width 1468.8, + :height 1900.8}, + :rects ({:x1 762.90625, + :y1 904.640625, + :x2 920.9835815429688, + :y2 935.640625, + :width 1468.8, + :height 1900.8}), + :page 4}, + :content {:text "Conflict aborts."}, + :properties {:color "yellow"}} + {:id #uuid "645271fa-ff04-4263-a2f2-d1879c1fb857", + :page 4, + :position {:bounding {:x1 762.90625, + :y1 1118.015625, + :x2 955.517822265625, + :y2 1149.015625, + :width 1468.8, + :height 1900.8}, + :rects ({:x1 762.90625, + :y1 1118.015625, + :x2 955.517822265625, + :y2 1149.015625, + :width 1468.8, + :height 1900.8}), + :page 4}, + :content {:text "Capacity aborts. "}, + :properties {:color "yellow"}} + {:id #uuid "64527248-77dc-4d32-8a2b-737b7329d2e9", + :page 4, + :position {:bounding {:x1 762.90625, + :y1 1245.3125, + :x2 901.3764038085938, + :y2 1276.3125, + :width 1468.8, + :height 1900.8}, + :rects ({:x1 762.90625, + :y1 1245.3125, + :x2 901.3764038085938, + :y2 1276.3125, + :width 1468.8, + :height 1900.8}), + :page 4}, + :content {:text "Other aborts."}, + :properties {:color "yellow"}} + {:id #uuid "64527270-d6d5-4232-98af-c0212ef47511", + :page 4, + :position {:bounding {:x1 762.90625, + :y1 1487.34375, + :x2 1138.2952880859375, + :y2 1525.34375, + :width 1468.8, + :height 1900.8}, + :rects ({:x1 762.90625, + :y1 1487.34375, + :x2 1138.2952880859375, + :y2 1525.34375, + :width 1468.8, + :height 1900.8} + {:x1 798.765625, + :y1 1492.34375, + :x2 827.4942016601562, + :y2 1521.03125, + :width 1468.8, + :height 1900.8}), + :page 4}, + :content {:text "2.4 HTM in PM File Systems"}, + :properties {:color "yellow"}} + {:id #uuid "6452774e-a951-480a-a890-322d30fe3fd0", + :page 5, + :position {:bounding {:x1 129.59375, + :y1 560.4375, + :x2 255.5180206298828, + :y2 598.4375, + :width 1468.8, + :height 1900.8}, + :rects ({:x1 129.59375, + :y1 560.4375, + :x2 255.5180206298828, + :y2 598.4375, + :width 1468.8, + :height 1900.8} + {:x1 143.9375, + :y1 565.4375, + :x2 172.66607666015625, + :y2 594.125, + :width 1468.8, + :height 1900.8}), + :page 5}, + :content {:text "3 Design"}, + :properties {:color "yellow"}} + {:id #uuid "645277dc-272c-4479-9d09-3f178cb77a42", + :page 5, + :position {:bounding {:x1 129.59375, + :y1 1253.6875, + :x2 256.3342590332031, + :y2 1291.6875, + :width 1468.8, + :height 1900.8}, + :rects ({:x1 129.59375, + :y1 1253.6875, + :x2 256.3342590332031, + :y2 1291.6875, + :width 1468.8, + :height 1900.8} + {:x1 165.453125, + :y1 1258.6875, + :x2 256.3342590332031, + :y2 1287.375, + :width 1468.8, + :height 1900.8}), + :page 5}, + :content {:text "3.1 HOP"}, :properties {:color "yellow"}}], - :extra {:page 2}} + :extra {:page 7}} diff --git a/journals/2023_04_30.md b/journals/2023_04_30.md index 6a6ff8e..480e83e 100644 --- a/journals/2023_04_30.md +++ b/journals/2023_04_30.md @@ -3,4 +3,5 @@ - 计组第五章看了快一半，明天应该能看完第五章 - 明天开始把论文看起来 - 抄写编译器前端 + - 究极抽象，代码量太大了，抄都不知道从哪里开始抄 - 论语报告完善了一下，估计是不会想再看第二遍了，这东西纯纯的尬写，我也不知道老师怎么看得下去的 \ No newline at end of file diff --git a/journals/2023_05_01.md b/journals/2023_05_01.md new file mode 100644 index 0000000..6cf35ef --- /dev/null +++ b/journals/2023_05_01.md @@ -0,0 +1,4 @@ +- 精神有点恍惚，可能是前两天睡眠不足，本来打算看论文的，结果绷不住了打游戏了 +- 终于把第五章看完了啊，第六章可能不会去看了 +- 继续抄写编译器前端 +- 出去吃了烤肉，感觉不如自助烤肉 \ No newline at end of file diff --git a/journals/2023_05_02.md b/journals/2023_05_02.md new file mode 100644 index 0000000..c936a20 --- /dev/null +++ b/journals/2023_05_02.md @@ -0,0 +1,3 @@ +- 编译器前端部分的框架姑且算是写完了，接下来就是无聊的堆代码环节 +- 模式识别作业写了一半不想写了，明天抄别人的 +- 看了看论文 \ No newline at end of file diff --git a/journals/2023_05_03.md b/journals/2023_05_03.md new file mode 100644 index 0000000..34f76bc --- /dev/null +++ b/journals/2023_05_03.md @@ -0,0 +1,4 @@ +- 作业算是糊完了 +- 莫名其妙生病了，早上七点肚子疼给整醒了，跑了6趟厕所然后睡到中午，早上没了 + - 吃了点氨酚烷胺又睡了一会，然后抄完了作业把报告写完已经九点了，五一莫名其妙就结束了，不过明天一节课、后天没课的我，结束没结束好像没啥区别 +- 继续低效看论文，编译器没动 \ No newline at end of file diff --git a/pages/hls__Computer_Organization_and_Design_1681729306797_0.md b/pages/hls__Computer_Organization_and_Design_1681729306797_0.md index 0f853ca..e8a9bdb 100644 --- a/pages/hls__Computer_Organization_and_Design_1681729306797_0.md +++ b/pages/hls__Computer_Organization_and_Design_1681729306797_0.md @@ -2165,21 +2165,507 @@ file-path:: ../../../../assets/Computer_Organization_and_Design_1681729306797_0. hl-page:: 492 hl-color:: yellow id:: 644e5adc-7d6c-4136-8fa7-7849417949da +- ## Dependable Memory Hierarchy + ls-type:: annotation + hl-page:: 497 + hl-color:: yellow + id:: 644dea78-9ad9-4322-a05d-1b30789b85a8 + collapsed:: true + - Two states of delivered service: Service accomplishment & Serviced interruption, which means delivered service is the same as/different from specified service + hl-page:: 497 + ls-type:: annotation + id:: 644f4473-da2b-4f3c-8d32-89b90b80f0b2 + hl-color:: yellow + - Transitions from state 1 to state 2 are caused by **failures**, and transitions from state2 to state 1 are called **restorations**. + hl-page:: 497 + ls-type:: annotation + id:: 644f4518-efff-41a8-8445-5b9e2434e9cd + hl-color:: yellow + - Failures can be permanent or intermittent. + ls-type:: annotation + hl-page:: 497 + hl-color:: yellow + id:: 644f4535-12cc-4669-bdbe-4d72b5066fae + - Reliability is a measure of the continuous service accomplishment. + hl-page:: 497 + ls-type:: annotation + id:: 644f456f-e4bb-44be-8352-ad557cd80060 + hl-color:: yellow + - **mean time to failure** (MTTF) and **annual failure rate** (AFR) + hl-page:: 497 + ls-type:: annotation + id:: 644f4583-1a89-4136-b6e8-ae34cd452815 + hl-color:: yellow + - How long you can use it before it fails + - Service interruption is measured as **mean time to repair** (MTTR). + hl-page:: 498 + ls-type:: annotation + id:: 644f45a7-aaf5-4489-bce0-cb66c22f42cf + hl-color:: yellow + - How long to repair it after it fails + - Mean time between failures (MTBF) is simply the sum of MTTF + MTTR + ls-type:: annotation + hl-page:: 498 + hl-color:: yellow + id:: 644f4623-bf70-495e-93f7-358fc369d438 + - Availability is a measure of service accomplishment with respect to the alternation between accomplishment and interruption. $\text{Avail}=\frac{\text{MTTF}}{\text{MTTF+MTTR}}$ + hl-page:: 498 + ls-type:: annotation + id:: 644f46aa-3ee6-4b4c-95c5-74c326fd758e + hl-color:: yellow + - To improve MTTF: Fault avoidance, Fault tolerance, Fault forecasting + hl-page:: 498 + ls-type:: annotation + id:: 644f4720-89b2-4fd5-813f-1a9f18579745 + hl-color:: yellow + - Hamming Code + - **Hamming distance**: the ==minimum number of different bits== between any two ==correct== bit patterns + hl-page:: 499 + ls-type:: annotation + id:: 644f47cb-b392-4558-a654-ce01bcf35209 + hl-color:: yellow + - **Parity code**: Count the number of 1s in a word, and append a parity bit when written into memory, say 1 for odd 1s and 0 for even 1s. Therefore, the parity of the N+1 bit word should always be even, otherwise, there must be an error. + hl-page:: 499 + ls-type:: annotation + id:: 644f48cc-4cf6-4eb8-96e5-93812335f425 + hl-color:: yellow + - Actually, a 1-bit parity scheme can detect any odd number of errors; however, the probability of having 3 or 5 errors is much lower than the probability of having 2 + hl-page:: 499 + ls-type:: annotation + id:: 644f497d-9fb1-4ec1-b8a0-845652868073 + hl-color:: yellow + - Hamming Error Correction Code (ECC) + ls-type:: annotation + hl-page:: 499 + hl-color:: yellow + id:: 644f49ab-9ec8-46f0-9dcb-86eb1da64df2 + - Add extra parity bits to identify the position of the single-bit error, and the word with parity bits has a Hamming distance of 3. + - For 8-bit data word, we need 4 parity bits, respectively placed at the 1,2,4,8th bit of the 12-bit code. + - For larger words, the number of parity bits can be calculated as $p \ge \log_2(p+d+1)$ + - See FIGURE 5.24 for detail + hl-page:: 500 + ls-type:: annotation + id:: 644f4df8-30ce-44fd-bc9f-973ccbb7fd6f + hl-color:: yellow + - Single error correction and Double error detection + hl-page:: 501 + ls-type:: annotation + id:: 644f4e40-7352-4c4a-9a9c-5bdfb79ada0a + hl-color:: yellow + - Make the code's hamming distance 4, by adding a parity bit for the whole code word. + - Also, see the textbook for detail + - - ## Virtual Machines ls-type:: annotation hl-page:: 503 hl-color:: yellow id:: 644e0550-6991-4b86-9765-612e71bed268 + collapsed:: true + - System Virtual Machines: run the same ISA as the native hardware + hl-page:: 503 + ls-type:: annotation + id:: 644f511d-3a0f-4204-acd0-40eca3d58610 + hl-color:: yellow + - A single computer, running multiple VMs, supporting multiple OSs and they share the hardware + - virtual machine monitor (VMM) or hypervisor + hl-page:: 503 + ls-type:: annotation + id:: 644f5195-6bdf-4db1-9e4a-5b4dbc959df6 + hl-color:: yellow + - host and guest + ls-type:: annotation + hl-page:: 503 + hl-color:: yellow + id:: 644f51a9-f75b-4d73-91dd-89fbaa91ffe9 + - protection, managing software, managing hardware + - The cost of processor virtualization depends on the workload. + hl-page:: 504 + ls-type:: annotation + id:: 644f5241-37dc-4efa-acc9-9ae8739b7e19 + hl-color:: yellow + - User-level processor-bound programs have 0 virtualization overhead, native speed + hl-page:: 504 + ls-type:: annotation + id:: 644f5287-cac6-46c8-ad60-8cee1ca0c57c + hl-color:: yellow + - I/O-intensive workloads, also OS-intensive, have high virtualization overhead. As many system calls and privileged instructions. + hl-page:: 504 + ls-type:: annotation + id:: 644f52a8-98fb-466b-92cf-7c0f942382b2 + hl-color:: yellow + - Requirements of a Virtual Machine Monitor + ls-type:: annotation + hl-page:: 505 + hl-color:: yellow + id:: 644f52db-8deb-4e8b-8a11-e59b2bbfbe26 + - Guest software should behave on a VM exactly as if it were running on the native hardware, + ls-type:: annotation + hl-page:: 505 + hl-color:: yellow + id:: 644f533e-a31c-4916-bb47-2c97eae78310 + - Guest software should not be able to change allocation of real system resources directly. + ls-type:: annotation + hl-page:: 505 + hl-color:: yellow + id:: 644f5340-0e7e-4ea2-b337-2779d4092da5 + - At least two processor modes, system and user. + ls-type:: annotation + hl-page:: 505 + hl-color:: yellow + id:: 644f5401-cfe8-439b-af2e-d91bc6dae442 + - A privileged subset of instructions that is available only in system mode; all system resources must be controllable only via these instructions. + ls-type:: annotation + hl-page:: 505 + hl-color:: yellow + id:: 644f5403-7aab-4e4e-ae71-87aa2d22bbbd +- ## Virtual Memory + ls-type:: annotation + hl-page:: 506 + hl-color:: yellow + id:: 644f4178-a1ca-40e3-b488-3ce044954e46 + collapsed:: true + - Making Address Translation Fast: the TLB + ls-type:: annotation + hl-page:: 517 + hl-color:: yellow + id:: 644f5d06-3450-4d12-96e5-374712790d9e + collapsed:: true + - TLB entry + - Tag holds a portion of the VPN, and data entry holds a PPN. + hl-page:: 517 + ls-type:: annotation + id:: 644f5d6e-0c4e-48ad-9284-7b6247cc3d15 + hl-color:: yellow + - TLB will need to include other status bits, such as the dirty and the reference bits. + hl-page:: 518 + ls-type:: annotation + id:: 644f5d87-be05-4020-a8e8-d23c4a0fcfa4 + hl-color:: yellow + - Cache-like considerations + - Write policy: write-back, since the miss rate is low + - Associativity: decided by the number of TLB entries + - Replacement: many systems provide some support for random replacement, because LRU are expensive to implement especially by hardware + hl-page:: 518 + ls-type:: annotation + id:: 644f5f4f-8fce-4a04-9ccc-eb988f0e3ed3 + hl-color:: yellow + - The Intrinsity FastMATH TLB + ls-type:: annotation + hl-page:: 519 + hl-color:: yellow + id:: 644f60f0-680e-4aa0-a0de-165342178045 + - 4K page and 32-bit AS lead to 20-bit VPN. Thus 20-bit tag, 20-bit data, and some other bookkeeping bits + - 16-way fully associative TLB, compare VPN against all tags + - On TLB miss, MIPS hardware saves the page number of the reference in a special register and raise exception. + hl-page:: 519 + ls-type:: annotation + id:: 644f61e2-eb58-44d5-8b89-b55c3708f25a + hl-color:: yellow + - The hardware maintains an index that indicates the recommended entry to replace, which is chosen randomly. + hl-page:: 519 + ls-type:: annotation + id:: 644f62bd-6a29-40bc-a634-15fed6bc1ec9 + hl-color:: yellow + - TLB miss routine in OS indexes the table with relevant registers. + - Using a special set of system instructions that can update the TLB, OS handler set replace an entry with the new entry fetched from memory + hl-page:: 519 + ls-type:: annotation + id:: 644f6250-82e1-4286-b25a-e4f4eb0eb622 + hl-color:: yellow + - A true page fault occurs if the PTE does not have a valid PA + hl-page:: 519 + ls-type:: annotation + id:: 644f62a6-7b6d-4434-bc3d-233892af468f + hl-color:: yellow + - Integrating Virtual Memory, TLBs, and Caches + ls-type:: annotation + hl-page:: 519 + hl-color:: yellow + id:: 644f6050-cd77-4d32-afdb-3bf8a90302b7 + collapsed:: true + - FIGURE 5.31 Processing a read or a write-through in the Intrinsity FastMATH TLB and cache. + ls-type:: annotation + hl-page:: 521 + hl-color:: yellow + id:: 644f60d4-72c9-41e9-b976-d1ed1c07d830 + - Cache and TLB + - In the simplest case, all memory addresses are translated to PAs before the cache access. This is slow. + hl-page:: 522 + ls-type:: annotation + id:: 644f6370-8fd9-4a5e-92e3-09b74f6baa04 + hl-color:: yellow + - Virtually addressed cache: uses tags from VAs, VIVT, to avoid using TLB before cache access (unless a TLB miss), which takes TLB out of critical path. + hl-page:: 522 + ls-type:: annotation + id:: 644f6397-14d2-491c-9cef-bbfd6e5cca8f + hl-color:: yellow + - Aliasing occurs when the same object has two names. In this case, 2 VAs for the same page. Then one physical page has two copies in cache, introducing consistency issue. + hl-page:: 523 + ls-type:: annotation + id:: 644f6434-eb87-405e-9190-4f67466af467 + hl-color:: yellow + - Common compromise: virtually indexed but physically tagged, VIPT. Use the page offset portion of the address, which is identical in VA and PA, as the index of cache. + hl-page:: 523 + ls-type:: annotation + id:: 644f6491-3e52-4db7-a824-5988e124ee1c + hl-color:: yellow + - Implementing Protection with Virtual Memory (Trivial) + hl-page:: 523 + ls-type:: annotation + id:: 644f65cf-03a5-4132-b091-e08b9ce9002a + hl-color:: yellow + collapsed:: true + - Requirement for Hardware + - Support at least 2 priority levels of process + - Provide a portion of the processor state that a user process can read but not write. + ls-type:: annotation + hl-page:: 523 + hl-color:: yellow + id:: 644f65f9-38a8-4ead-90f5-494c0b2e3191 + - Provide mechanisms whereby the processor can go from user mode to supervisor mode and vice versa. In MIPS, `syscall` and `eret` + hl-page:: 524 + ls-type:: annotation + id:: 644f660f-7534-4124-9b7e-32cd2ce2c77a + hl-color:: yellow + - Handling TLB Misses and Page Faults + ls-type:: annotation + hl-page:: 525 + hl-color:: yellow + id:: 644f65b8-c079-42ce-a6b6-e1c56dbf45e9 + - TLB miss can indicate one of two possibilities: Page in memory and True page fault + hl-page:: 525 + ls-type:: annotation + id:: 644f67c6-de09-4546-b3a6-cbb286cca5bb + hl-color:: yellow + - MIPS handles a TLB miss in software. It brings in PTE from memory and then re-executes the instruction that caused the TLB miss. Upon re-executing, it will get a TLB hit. + hl-page:: 525 + ls-type:: annotation + id:: 644f6897-2635-4cb9-ae6b-2515dc05694b + hl-color:: yellow + - We must prevent load/store from actually completing when there is an exception, when implementing the pipeline + hl-page:: 526 + ls-type:: annotation + id:: 644f68df-1f9b-4430-a2ea-09ee1ca7361f + hl-color:: yellow + - General process of TLB handling + - Upon a TLB miss, the MIPS hardware saves the page number of the reference in `BadVAddr` and generates exception. + hl-page:: 527 + ls-type:: annotation + id:: 644f6974-151b-46fa-afe2-ceed4ec48722 + hl-color:: yellow + - Control is transferred to address `0x8000_0000`, the location of the TLB miss handler. + hl-page:: 528 + ls-type:: annotation + id:: 644f69a6-31f7-4f57-8c78-75a19f0d83fd + hl-color:: yellow + - MIPS hardware places everything you need in the `Context` register: `base of page table | VPN` + hl-page:: 528 + ls-type:: annotation + id:: 644f69dd-753d-4df6-b0fc-4f112a12f0ce + hl-color:: yellow + - Since TLB misses are quite frequent, the handler is simple + ```asm + TLBmiss: + mfc0 $k1,Context # copy address of PTE into temp $k1 + lw $k1,0($k1) # put PTE into temp $k1 + mtc0 $k1,EntryLo # put PTE into special register EntryLo + tlbwr # put EntryLo into TLB entry at Random + eret # return from TLB miss exception + ``` + - TLB miss routine does not check validity of the page, but rather directly loads the PTE into TLB. If it is a true page fault, let the processor generate the Page Fault exception. + - TLB miss routine does not save process state, since it doesn't need to change anything + - TLB miss has a separate handler address, saving the effort to diagnose exception type from `Cause` register + - The process of handling a page fault is laborious. See FIGURE 5.34 for detail. + hl-page:: 530 + ls-type:: annotation + id:: 644f6cf2-142f-4b34-a4c1-06de2a87879a + hl-color:: yellow + - To avoid the problem of a page fault during this low-level exception code, MIPS sets aside a portion of its address space that cannot have page faults, called `unmapped`. + hl-page:: 529 + ls-type:: annotation + id:: 644f6d39-ad59-4a15-81a9-8dede8bef344 + hl-color:: yellow + - Aside: The VMM implements memory control by maintaining a shadow page table. See textbook for detail + hl-page:: 529 + ls-type:: annotation + id:: 644f6d8d-7c2f-4cb7-b689-eb282d35f411 + hl-color:: yellow - ## A Common Framework for Memory Hierarchy ls-type:: annotation hl-page:: 533 hl-color:: yellow id:: 644e610b-15ef-47cd-8701-7bf7be87f16c + collapsed:: true + - Question 1: Where Can a Block Be Placed? + ls-type:: annotation + hl-page:: 534 + hl-color:: yellow + id:: 644f6e31-ed3f-4bbf-8f30-53fe28e9e518 + - This entire range of schemes can be thought of as variations on a set-associative scheme where the number of sets and the number of blocks per set varies + hl-page:: 534 + ls-type:: annotation + id:: 644f6e76-bf1e-4def-b9c0-75f1faf3b5c6 + hl-color:: yellow + - As cache size grows, the benefit of increasing associativity is slight. + - Question 2: How Is a Block Found? + ls-type:: annotation + hl-page:: 535 + hl-color:: yellow + id:: 644f6ec3-e710-4abf-94a2-9f0c362e40e8 + - VM uses full associative, while cache/TLB uses set associative + - Question 3: Which Block Should Be Replaced on a Cache Miss? + ls-type:: annotation + hl-page:: 536 + hl-color:: yellow + id:: 644f6f0b-c5e3-4c38-90ec-67e3118b5c3d + - For hardware, random or approximated LRU, since they are simple to build + - In virtual memory, some form of LRU is always approximated, in that miss penalty is significant + hl-page:: 536 + ls-type:: annotation + id:: 644f6f9a-a898-4b20-88c0-588c940ec793 + hl-color:: yellow + - Question 4: What Happens on a Write? + ls-type:: annotation + hl-page:: 536 + hl-color:: yellow + id:: 644f6fd5-59c8-41e3-8ede-402475ac6a72 + - A summary of pros and cons for Write-back and Write-through + - When write latency is unacceptable, we tend to use Write-back + - The Three Cs: An Intuitive Model for Understanding the Behavior of Memory Hierarchies + ls-type:: annotation + hl-page:: 538 + hl-color:: yellow + id:: 644f6ffe-256a-4252-af5b-5a2a8d03fc2e + - Compulsory, Capacity and Conflict misses + - Note that, compulsory misses can be reduced by increasing the block size +- ## Using a Finite-State Machine to Control a Simple Cache + ls-type:: annotation + hl-page:: 540 + hl-color:: yellow + id:: 644f418c-dea9-442d-9f38-a60aef123e15 + collapsed:: true + - Settings: Direct-mapped, Write-back and write-allocate, 16-Byte block, 16-KB total + - 10-bit Index, 4-bit Offset, 18-bit Tag + - Signals: 2 sets of signals, respectively CPU-Cache and Cache-Memory + - Read/Write, Valid, Address, Read data, Write data, Ready + - FSM for a Simple Cache Controller + ls-type:: annotation + hl-page:: 543 + hl-color:: yellow + id:: 644f731a-a08e-4b86-ace7-800cf640accb + - Idle: Waits for a valid CPU request + - Compare Tag + - Test hit or miss: Select block with the index field, and then compare the tag, last check valid. + - If hit, set `CacheReady` and go back to Idle. If write, set the dirty bit; If read, set the `ReadData` + - If miss, set tag of the victim block to required address. Then go to Allocate or Write-back, determined by the dirty bit + - Note that, this state can be split into compare and access, to reduce latency + - Write-back: Writes a block to Memory (and wait for Memory's write ready). On completion, go to Allocate (since we have to wait for new data). + - Allocate: Waits for the Ready signal from Memory. On completion, goes to Compare Tag. +- ## Parallelism and Memory Hierarchy: Cache Coherence + ls-type:: annotation + hl-page:: 545 + hl-color:: yellow + id:: 644f41a2-4c7b-4b27-b75e-ea06924fa51e + - **Coherence** defines what values can be returned by a read + hl-page:: 545 + ls-type:: annotation + id:: 644f76e2-d5bc-47b0-90dd-c7ff33f07f13 + hl-color:: yellow + - A memory system is coherent if: + hl-page:: 545 + ls-type:: annotation + id:: 644f77a6-d507-4b1a-bc25-7f42648fd943 + hl-color:: yellow + - A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P. + ls-type:: annotation + hl-page:: 545 + hl-color:: yellow + id:: 644f77b5-83a5-4fb1-b3a6-3a2db489da39 + - A read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses. + ls-type:: annotation + hl-page:: 545 + hl-color:: yellow + id:: 644f77c2-e346-4ffc-bb20-a1b3933fe9fc + - Writes to the same location are serialized; that is, two writes to the same location by any two processors are seen in the same order by all processors. + ls-type:: annotation + hl-page:: 546 + hl-color:: yellow + id:: 644f77ca-4b61-4296-8a04-a7781102a0a2 + - **Consistency** determines when a written value will be returned by a read. + hl-page:: 545 + ls-type:: annotation + id:: 644f76e7-a61d-4f42-9c8a-adc7eb920a8c + hl-color:: yellow + - Basic Schemes for Enforcing Coherence + ls-type:: annotation + hl-page:: 546 + hl-color:: yellow + id:: 644f7883-18c3-43d5-a7ed-51fac0fb3d83 + - Migration: A data item can be moved to a local cache and used there in a transparent fashion. + ls-type:: annotation + hl-page:: 546 + hl-color:: yellow + id:: 644f78a3-7065-435c-8ee6-21ae194c1961 + - Replication: When shared data are being ==simultaneously read==, the caches make a copy of the data item in the local cache. + ls-type:: annotation + hl-page:: 547 + hl-color:: yellow + id:: 644f78b7-c9fa-4854-824d-a8d0952ad3be + - cache coherence protocols, tracking the state of any sharing of a data block + hl-page:: 547 + ls-type:: annotation + id:: 644f7956-11ad-4140-b966-6d2061ae6fb2 + hl-color:: yellow + - snooping + ls-type:: annotation + hl-page:: 547 + hl-color:: yellow + id:: 644f7a3d-783f-49d2-b697-91200284b2c8 + - For each block, the caches which have this block, hold both the copy of data and a copy of the sharing status of this block. + - caches are accessible via some broadcast medium + hl-page:: 547 + ls-type:: annotation + id:: 644f7ab7-b97c-41a9-8780-e9281ab19565 + hl-color:: yellow + - cache controllers monitor (snoop) on the medium, to determine whether they have a copy of a block that is requested on a bus or switch access. + hl-page:: 547 + ls-type:: annotation + id:: 644f7ad5-2103-4b23-a6c0-0417d431eb02 + hl-color:: yellow + - write invalidate protocol: invalidate copies in other caches on a write. When others want to read/write later, they miss and fetch from memory. When others want to write simultaneously, there is a race and there is always a winner. + hl-page:: 547 + ls-type:: annotation + id:: 644f797d-e82e-49fc-97b0-df7034494d5f + hl-color:: yellow + - ensure that a processor has exclusive access to a data item before it writes that item +- Parallelism and the Memory Hierarchy: Redundant Arrays of Inexpensive Disks + hl-page:: 550 + ls-type:: annotation + id:: 644f41d0-39d8-476b-8d62-08e2bf5979ef + hl-color:: yellow + collapsed:: true + - Refer to ((6437e8b0-b179-46c1-9173-e9b080273f7e)) - ## Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies ls-type:: annotation hl-page:: 557 hl-color:: yellow id:: 644e0503-5ee5-4da8-bf62-04b2fa91e5f9 + collapsed:: true + - To support multiple issue (fetch more instructions per cycle), a popular technique is to break the cache into banks and allow multiple, independent, parallel accesses (if the addresses are in different banks). + hl-page:: 558 + ls-type:: annotation + id:: 644fae8b-080a-4bed-8e02-08519a34b547 + hl-color:: yellow + - nonblocking cache: *Hit under miss* allows additional cache hits during a miss, while *miss under miss* allows multiple outstanding cache misses. + hl-page:: 558 + ls-type:: annotation + id:: 644faeff-a7cf-4a48-b257-50e090ca62be + hl-color:: yellow + - Core i7 has prefetch mechanism for data accesses + hl-page:: 559 + ls-type:: annotation + id:: 644faf31-abe7-4938-b43a-15ca77c5a20a + hl-color:: yellow - Going Faster: Cache Blocking and Matrix Multiply ls-type:: annotation hl-page:: 561 @@ -2190,25 +2676,59 @@ file-path:: ../../../../assets/Computer_Organization_and_Design_1681729306797_0. hl-page:: 564 hl-color:: yellow id:: 644deab8-5929-424b-a0bb-9944268d757e -- Word List 5 - collapsed:: true - - rug + - Pitfall: Having less set associativity for a shared cache than the number of cores or threads sharing that cache. ls-type:: annotation + hl-page:: 565 + hl-color:: yellow + id:: 644fb0df-1bf0-479c-bb16-de1b6729faa4 +- Word List 5 + - rug 小块地毯 hl-page:: 462 - hl-color:: green + ls-type:: annotation id:: 644dded8-ffe3-4d2e-abbe-d4374b5b30af - - proximity + hl-color:: green + - proximity (时间或空间)接近,邻近,靠近: ls-type:: annotation hl-page:: 478 hl-color:: green id:: 644e0631-3612-4778-86c2-e6f062b426ab - - incur - ls-type:: annotation + - incur 招致，引发；蒙受 hl-page:: 489 - hl-color:: green + ls-type:: annotation id:: 644e59e3-12be-418f-bd07-bb228ec2a8ac -- ## Dependable Memory Hierarchy + hl-color:: green + - Voila 〈法〉那就是,瞧(表示事情成功或满意之感叹词用语) + hl-page:: 501 + ls-type:: annotation + id:: 644f4c11-76c4-4c50-8278-f5a18415cad6 + hl-color:: green + - culprit 罪犯；肇事者 + hl-page:: 505 + ls-type:: annotation + id:: 644f5381-dd30-4674-b37e-ce080e71a4a2 + hl-color:: green + - duality 二元性； + hl-page:: 515 + ls-type:: annotation + id:: 644f5b71-6ca0-47f3-8a20-9cc15c1fa0e0 + hl-color:: green + - simplistic 过分简单化的 + hl-page:: 545 + ls-type:: annotation + id:: 644f7695-12e8-4ffe-a6c7-105b596300de + hl-color:: green + - saga 冒险故事；传说；英雄事迹 + ls-type:: annotation + hl-page:: 561 + hl-color:: green + id:: 644fafd9-52b6-4378-b808-35d07dd67108 + - underscore 下画线 + hl-page:: 568 + ls-type:: annotation + id:: 644fb0c3-4e0b-41ea-8edb-01e11b936c65 + hl-color:: green +- # Parallel Processors from Client to Cloud ls-type:: annotation - hl-page:: 497 + hl-page:: 586 hl-color:: yellow - id:: 644dea78-9ad9-4322-a05d-1b30789b85a8 \ No newline at end of file + id:: 644fb152-58ba-4049-b461-37264438cfde \ No newline at end of file diff --git a/pages/hls__HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871_0.md b/pages/hls__HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871_0.md index d979402..dbd8bbb 100644 --- a/pages/hls__HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871_0.md +++ b/pages/hls__HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871_0.md @@ -13,4 +13,115 @@ file-path:: ../assets/HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871 id:: 644b2866-2f98-49f4-a914-2d1400d47e3b - Earlier FSs optimize for performance, but provide loose consistency guarantees - With the speedup of modern storage devices, strong consistency can ease the pain of software programming. - - Strong consistency implies per-request sequential consistency. \ No newline at end of file + - Strong consistency implies per-request sequential consistency. + - atomic modification: inode level locks + - Transaction semantics after crash recovery, all-or-none + - modern storage devices, PMEM, or non-volatile RAM + hl-page:: 2 + ls-type:: annotation + id:: 64511829-234d-45a3-9d1c-f50d60466704 + hl-color:: yellow + - Problem with existent PM FS: complicated mechanism, write amplification + - Previous approaches are limited to atomicity unit of CPU writes. + ls-type:: annotation + hl-page:: 2 + hl-color:: yellow + id:: 64511979-cee9-4f46-87ba-6bbfe86bf0a4 + - Problem with RTM: Block IO abort RTM; PM can be accessed as RAM, but with cache involved, also abort RTM + - enhanced asynchronous DRAM refresh (eADR) + hl-page:: 3 + ls-type:: annotation + id:: 64511f4c-4338-41ad-9264-263ed5a08bf4 + hl-color:: yellow + - guarantee the persistence of memory writes once they become globally visible, + ls-type:: annotation + hl-page:: 3 + hl-color:: yellow + id:: 6451204b-d1b8-46ed-8ec9-3a7c2d05244e + - eliminate the need for cache flush to sync with PM + - See [Detail](https://www.intel.com/content/www/us/en/developer/articles/technical/eadr-new-opportunities-for-persistent-memory-applications.html) + - Several challenges with RTM-PM + hl-page:: 3 + ls-type:: annotation + id:: 6451205e-7f48-43e8-8704-d221d806cc18 + hl-color:: yellow + - RTM is small, while FS data transfer are generally large + - Some FS operations have long code-path, lengthening RTM section, increasing conflict abort rate + - Hardware-assisted Optimistic Persistence + ls-type:: annotation + hl-page:: 3 + hl-color:: yellow + id:: 64512109-8ab0-49aa-b6a3-1524df0631ef + - eADR, HTM with cooperative locks as fallback + - HTMFS, a user-space PM file systems base on ZoFS + ls-type:: annotation + hl-page:: 3 + hl-color:: yellow + id:: 64512150-84a0-4839-aef6-48bb872fa776 +- Background and Motivation + ls-type:: annotation + hl-page:: 3 + hl-color:: yellow + id:: 6451215b-a495-4d6f-9427-f5c0c6685a28 + - Persistent Memory and PM File Systems + ls-type:: annotation + hl-page:: 4 + hl-color:: yellow + id:: 645124e7-37ae-404c-bc83-2ae78628767f + - 主要的点就是，PM 是 ==byte-addressable== + - Existing PMFS: The only difference would be leveraging atomic instructions to provide small updates up to a single cache line + hl-page:: 4 + ls-type:: annotation + id:: 64526ec1-37e2-4891-bba8-eeb07c6e02d3 + hl-color:: yellow + - 作者认为现有的PMFS没啥创新，在一致性上还是用的旧东西，除了用 PM 提供的 atomic inst 来简化某些原子操作 + - 2.3 Hardware Transactional Memory + ls-type:: annotation + hl-page:: 4 + hl-color:: yellow + id:: 6452709d-6036-4dcd-8821-c106562565fe + - RTM的基本用法：把 critical section 用 `xbegin` 和 `xend` 包起来 + hl-page:: 4 + ls-type:: annotation + id:: 645270e0-2153-4414-8b22-762cfc113c19 + hl-color:: yellow + - Conflict aborts + hl-page:: 4 + ls-type:: annotation + id:: 64527149-e50e-46c8-990f-0465060f9a5a + hl-color:: yellow + - 硬件维护trx的 read set 和 write set，如果在提交之前，有别的 core 读 write set 或者写 read set，就会 abort。这些东西都在 cache 里面，维护这些也是用 cache coherence protocol + - Capacity aborts. + ls-type:: annotation + hl-page:: 4 + hl-color:: yellow + id:: 645271fa-ff04-4263-a2f2-d1879c1fb857 + - 受到每个core本地cache比如L1，的大小的限制 + - Other aborts + hl-page:: 4 + ls-type:: annotation + id:: 64527248-77dc-4d32-8a2b-737b7329d2e9 + hl-color:: yellow + - 不兼容指令，中断（所以打IO显然不行）等东西 + - 2.4 HTM in PM File Systems + ls-type:: annotation + hl-page:: 4 + hl-color:: yellow + id:: 64527270-d6d5-4232-98af-c0212ef47511 + - HTM的操作是在 cache 里面的，没有持久化保证，除非显式刷到内存/PM里。但是 临界区内不能刷（刷了就abort），临界区之后要是被切走就寄了（除非上锁，不如直接上锁） + - Intel 的新东西表示，它可以做到commit到cache里面就能持久化 +- 3 Design + ls-type:: annotation + hl-page:: 5 + hl-color:: yellow + id:: 6452774e-a951-480a-a890-322d30fe3fd0 + - 直接把 FS 操作用HTM包起来不现实，因为FS的操作都很长很大 + - 3.1 HOP + ls-type:: annotation + hl-page:: 5 + hl-color:: yellow + id:: 645277dc-272c-4479-9d09-3f178cb77a42 + - 非常自然的想法：把一个操作，或者说trx，拆成小的 + - 三种操作分类： + - Read、Invisible write(内部的东西，比如块分配信息) 、Visible write(应用程序可见的) + - 只有 Visible Write 用 HTM 实现，Invisible 和 Read 通过别的机制来实现 \ No newline at end of file diff --git a/pages/hls__ostep_1681115599584_0.md b/pages/hls__ostep_1681115599584_0.md index 95f4eed..90459ff 100644 --- a/pages/hls__ostep_1681115599584_0.md +++ b/pages/hls__ostep_1681115599584_0.md @@ -1028,6 +1028,7 @@ file-path:: ../assets/ostep_1681115599584_0.pdf hl-color:: yellow collapsed:: true - RAID Interface + id:: 643e8edc-8d60-4c99-ac89-8fb4720a1ac4 - Look like a ==big, fast and reliable disk==, which provides an abstraction of ==a linear array of blocks==. Usually, a RAID is connected to the host through ==standard interfaces== (e.g. SATA) - Internally, the RAID controller decides how to perform ==physical I/Os== in order to complete a single ==logical I/O==. - At a high level, a RAID is very much a specialized computer system: it has a processor, memory, and disks; however, instead of running applications, it runs specialized software designed to operate the RAID.