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LogSeq/assets/Computer_Organization_and_Design_1681729306797_0.edn
ridethepig 47053d35da quite a lot update
2023-05-04 10:59:09 +08:00

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:content {:text "inary bit patterns above are simply representatives of numbers. "},
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:content {:text "This trick works because positive two’s complement numbers really have an infinite number of 0s on the left and negative two’s complement numbers have an infinite number of 1s. The binary bit pattern representing a number hides leading bits to fit the width of the hardware; sign extension simply restores some of them."},
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:content {:text "Design Principle 3: Good design demands good compromises."},
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:content {:text "Design Principle 1: Simplicity favors regularity."},
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:content {:text "Instructions for Making Decisions"},
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:content {:text "conditional branches"},
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:content {:text "Supporting Procedures in Computer Hardware"},
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:content {:text "dichotomy "},
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:content {:text "Case/Switch Statement"},
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:content {:text "FIGURE 2.11 What is and what is not preserved across a procedure call. "},
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:content {:text " wax and wane."},
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:content {:text "Allocating Space for New Data on the Stack"},
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:content {:text "procedure frame or activation record"},
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:content {:text "Communicating with People"},
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:content {:text "MIPS Addressing for 32-bit Immediates and Addresses"},
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:content {:text "s multiple floating-point operands to be packed into a single128-bit SSE2 register"},
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:content {:text "FIGURE 4.1 An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them."},
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:content {:text "ate elements completely characterize the computer. "},
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:content {:text "ALU, which takes two 32-bit inputs and produces a 32-bit result, as well as a 1-bit signal if the result is "},
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:content {:text "load word and store word instructions"},
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:content {:text "The beq instruction has three operands"},
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:content {:text "Creating a Single Datapath"},
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:content {:text "A Simple Implementation Scheme"},
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:content {:text "ttempt to execute all instructions in one clock cycle. This means that no datapath resource can be used more than once per instruction"},
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:content {:text "To share a datapath element between two different instruction classes, we may need to allow multiple connections to the input of an element, using a multiplexor and control signal to select among the multiple inputs."},
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:content {:text "FIGURE 4.11 The simple datapath for the core MIPS architecture combines the elements required by different instruction classes. "},
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:content {:text "The ALU Control"},
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:content {:text "Designing the Main Control Unit"},
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:content {:text "An Overview of Pipelining"},
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:content {:text "anatomy "},
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:content {:text "Why a Single-Cycle Implementation Is Not Used Today"},
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:content {:text "Because we must assume that the clock cycle is equal to the worst-case delay for all instructions"},
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:content {:text "Under ideal conditions and with a large number of instructions, the speed-up from pipelining is approximately equal to the number of pipe stages; "},
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:content {:text " the hardware cannot support the combination of instructions that we want to execute in the same clock cycle"},
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:content {:text " the need to make a decision based on the results of one instruction while others are executing."},
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:content {:text " To retain the value of an individual instruction for its other four stages, the value read from instruction memory must be saved in a register."},
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:content {:text "any information needed in a later pipe stage must be passed to that stage via a pipeline register"},
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:content {:text "each logical component of the datapath—such as instruction memory, register read ports, ALU, data memory, and register write port—can be used only within a single pipeline stage. Otherwise, we would have a structural hazard"},
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:content {:text "multiple exceptions can occur simultaneously in a single clock cycle. The solution is to prioritize the exceptions so that it is easy to determine which is serviced first."},
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:content {:text "orrect single bit errors and detect double bit errors"},
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:content {:text "System Virtual Machines"},
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:content {:text "The underlying hardware platform is called the host, and its resources are shared among the guest VMs. "},
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:content {:text "the cost of processor virtualization depends on the workload."},
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:content {:text "A privileged subset of instructions that is available only in system mode, resulting in a trap if executed in user mode; all system resources must be controllable only via these instructions."},
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:content {:text "FIGURE 5.31 Processing a read or a write-through in the Intrinsity FastMATH TLB and cache."},
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:content {:text "The Intrinsity FastMATH TLB"},
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:content {:text ". When a TLB miss occurs, the MIPS hardware saves the page number of the reference in a special register and generates an exception. "},
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:content {:text "Using a special set of system instructions that can update the TLB, the operating system places the physical address from the page table into the TLB"},
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:content {:text " The hardware maintains an index that indicates the recommended entry to replace; the recommended entry is chosen randomly."},
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:content {:text "all memory addresses are translated to physical addresses before the cache is accessed"},
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:content {:text "aliasing. Aliasing occurs when the same object has two names—in this case, two virtual addresses for the same page."},
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:content {:text "common compromise between these two design points is caches that are virtually indexed"},
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:content {:text "Handling TLB Misses and Page Faults"},
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:content {:text "Implementing Protection with Virtual Memory"},
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:content {:text "Provide a portion of the processor state that a user process can read but not write."},
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:content {:text "Provide mechanisms whereby the processor can go from user mode to supervisor mode and vice versa. T"},
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:content {:text " a TLB miss can indicate one of two possibilities:"},
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:content {:text "MIPS traditionally handles a TLB miss in software. It brings in the page table entry from memory and then re-executes the instruction that caused the TLB miss. Upon re-executing, it will get a TLB hit. "},
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:content {:text " We must prevent the write into memory from actually completing when there is a page fault; "},
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:content {:text "S. When a TLB miss occurs, the MIPS hardware saves the page number of the reference in a special register called BadVAddr and generates an exception."},
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:content {:text "Control is transferred to address 8000 0000 hex, the location of the TLB miss handler."},
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:content {:text " MIPS hardware places everything you need in the special Context register"},
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:content {:text "FIGURE 5.34 MIPS code to save and restore state on an exception."},
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:content {:text "To avoid the problem of a page fault during this low-level exception code, MIPS sets aside a portion of its address space that cannot have page faults, called unmapped. "},
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:content {:text "he VMM maintains a shadow page table "},
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:content {:text ". As mentioned above, this entire range of schemes can be thought of as variations on a set-associative scheme where the number of sets and the number of blocks per set varies"},
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:content {:text "Question 3: Which Block Should Be Replaced on a Cache Miss?"},
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:content {:text "The Three Cs: An Intuitive Model for Understanding the Behavior of Memory Hierarchies"},
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:content {:text "cache coherence protocols."},
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:content {:text "ll cache controllers monitor or snoop on the medium to determine whether or not they have a copy of a block that is requested on a bus or switch access."},
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