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ridethepig c93527fb07 COD Chapter 4
2023-05-04 10:59:09 +08:00

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:content {:text "inary bit patterns above are simply representatives of numbers. "},
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:content {:text "This trick works because positive two’s complement numbers really have an infinite number of 0s on the left and negative two’s complement numbers have an infinite number of 1s. The binary bit pattern representing a number hides leading bits to fit the width of the hardware; sign extension simply restores some of them."},
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:content {:text "Design Principle 3: Good design demands good compromises."},
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:content {:text "Design Principle 1: Simplicity favors regularity."},
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:content {:text "Instructions for Making Decisions"},
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:content {:text "conditional branches"},
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:content {:text "Supporting Procedures in Computer Hardware"},
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:content {:text "dichotomy "},
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:content {:text "Case/Switch Statement"},
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:content {:text "FIGURE 2.11 What is and what is not preserved across a procedure call. "},
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:content {:text " wax and wane."},
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:content {:text "Allocating Space for New Data on the Stack"},
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:content {:text "procedure frame or activation record"},
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:content {:text "Communicating with People"},
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:content {:text "MIPS Addressing for 32-bit Immediates and Addresses"},
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:content {:text "Addressing in Branches and Jumps"},
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:content {:text "s multiple floating-point operands to be packed into a single128-bit SSE2 register"},
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:content {:text "Introduction"},
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:content {:text "FIGURE 4.1 An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them."},
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:content {:text "ate elements completely characterize the computer. "},
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:content {:text "ALU, which takes two 32-bit inputs and produces a 32-bit result, as well as a 1-bit signal if the result is "},
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:content {:text "load word and store word instructions"},
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:content {:text "The beq instruction has three operands"},
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:content {:text "Creating a Single Datapath"},
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:content {:text "ttempt to execute all instructions in one clock cycle. This means that no datapath resource can be used more than once per instruction"},
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:content {:text "To share a datapath element between two different instruction classes, we may need to allow multiple connections to the input of an element, using a multiplexor and control signal to select among the multiple inputs."},
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:content {:text "FIGURE 4.11 The simple datapath for the core MIPS architecture combines the elements required by different instruction classes. "},
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:content {:text "Because we must assume that the clock cycle is equal to the worst-case delay for all instructions"},
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:content {:text "Under ideal conditions and with a large number of instructions, the speed-up from pipelining is approximately equal to the number of pipe stages; "},
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:content {:text " the hardware cannot support the combination of instructions that we want to execute in the same clock cycle"},
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:content {:text " the need to make a decision based on the results of one instruction while others are executing."},
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:content {:text " To retain the value of an individual instruction for its other four stages, the value read from instruction memory must be saved in a register."},
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:content {:text "any information needed in a later pipe stage must be passed to that stage via a pipeline register"},
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:content {:text "each logical component of the datapath—such as instruction memory, register read ports, ALU, data memory, and register write port—can be used only within a single pipeline stage. Otherwise, we would have a structural hazard"},
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:content {:text "multiple exceptions can occur simultaneously in a single clock cycle. The solution is to prioritize the exceptions so that it is easy to determine which is serviced first."},
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:content {:text "set associative. In a set-associative cache, there are a fixed number of locations where each block can be placed."},
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:content {:text ". Going from one-way to two-way associativity decreases the miss rate by about 15%, but there is little further improvement in going to higher associativity."},
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:content {:text "The three portions of an address"},
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:content {:text "Reducing the Miss Penalty Using Multilevel Caches"},
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