60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
#include "types.h"
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#include "param.h"
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#include "memlayout.h"
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#include "riscv.h"
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#include "defs.h"
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//
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// the riscv Platform Level Interrupt Controller (PLIC).
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//
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void
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plicinit(void)
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{
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// set desired IRQ priorities non-zero (otherwise disabled).
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*(uint32*)(PLIC + UART0_IRQ*4) = 1;
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*(uint32*)(PLIC + VIRTIO0_IRQ*4) = 1;
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#ifdef LAB_NET
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// PCIE IRQs are 32 to 35
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for(int irq = 1; irq < 0x35; irq++){
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*(uint32*)(PLIC + irq*4) = 1;
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}
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#endif
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}
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void
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plicinithart(void)
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{
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int hart = cpuid();
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// set enable bits for this hart's S-mode
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// for the uart and virtio disk.
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*(uint32*)PLIC_SENABLE(hart) = (1 << UART0_IRQ) | (1 << VIRTIO0_IRQ);
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#ifdef LAB_NET
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// hack to get at next 32 IRQs for e1000
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*(uint32*)(PLIC_SENABLE(hart)+4) = 0xffffffff;
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#endif
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// set this hart's S-mode priority threshold to 0.
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*(uint32*)PLIC_SPRIORITY(hart) = 0;
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}
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// ask the PLIC what interrupt we should serve.
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int
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plic_claim(void)
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{
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int hart = cpuid();
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int irq = *(uint32*)PLIC_SCLAIM(hart);
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return irq;
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}
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// tell the PLIC we've served this IRQ.
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void
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plic_complete(int irq)
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{
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int hart = cpuid();
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*(uint32*)PLIC_SCLAIM(hart) = irq;
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}
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