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quite a lot update

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ridethepig 2023-05-04 10:54:25 +08:00
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assets/Computer_Organization_and_Design_1681729306797_0.edn
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assets/HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871_0.edn
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:content {:text " guarantee the persistence of memory writes once they become globally visible, "},
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:content {:text "everal challenges prevent RTM-PM "},
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- 计组第五章看了快一半，明天应该能看完第五章
- 明天开始把论文看起来
- 抄写编译器前端
- 究极抽象，代码量太大了，抄都不知道从哪里开始抄
- 论语报告完善了一下，估计是不会想再看第二遍了，这东西纯纯的尬写，我也不知道老师怎么看得下去的

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- 精神有点恍惚，可能是前两天睡眠不足，本来打算看论文的，结果绷不住了打游戏了
- 终于把第五章看完了啊，第六章可能不会去看了
- 继续抄写编译器前端
- 出去吃了烤肉，感觉不如自助烤肉

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- 编译器前端部分的框架姑且算是写完了，接下来就是无聊的堆代码环节
- 模式识别作业写了一半不想写了，明天抄别人的
- 看了看论文

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- 作业算是糊完了
- 莫名其妙生病了，早上七点肚子疼给整醒了，跑了6趟厕所然后睡到中午，早上没了
- 吃了点氨酚烷胺又睡了一会，然后抄完了作业把报告写完已经九点了，五一莫名其妙就结束了，不过明天一节课、后天没课的我，结束没结束好像没啥区别
- 继续低效看论文，编译器没动

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- ## Dependable Memory Hierarchy
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- Two states of delivered service: Service accomplishment & Serviced interruption, which means delivered service is the same as/different from specified service
hl-page:: 497
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- Transitions from state 1 to state 2 are caused by **failures**, and transitions from state2 to state 1 are called **restorations**.
hl-page:: 497
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- Failures can be permanent or intermittent.
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- **mean time to failure** (MTTF) and **annual failure rate** (AFR)
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- How long you can use it before it fails
- Service interruption is measured as **mean time to repair** (MTTR).
hl-page:: 498
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- How long to repair it after it fails
- Mean time between failures (MTBF) is simply the sum of MTTF + MTTR
ls-type:: annotation
hl-page:: 498
hl-color:: yellow
id:: 644f4623-bf70-495e-93f7-358fc369d438
- Availability is a measure of service accomplishment with respect to the alternation between accomplishment and interruption. $\text{Avail}=\frac{\text{MTTF}}{\text{MTTF+MTTR}}$
hl-page:: 498
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- To improve MTTF: Fault avoidance, Fault tolerance, Fault forecasting
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- Hamming Code
- **Hamming distance**: the ==minimum number of different bits== between any two ==correct== bit patterns
hl-page:: 499
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- **Parity code**: Count the number of 1s in a word, and append a parity bit when written into memory, say 1 for odd 1s and 0 for even 1s. Therefore, the parity of the N+1 bit word should always be even, otherwise, there must be an error.
hl-page:: 499
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id:: 644f48cc-4cf6-4eb8-96e5-93812335f425
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- Actually, a 1-bit parity scheme can detect any odd number of errors; however, the probability of having 3 or 5 errors is much lower than the probability of having 2
hl-page:: 499
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id:: 644f497d-9fb1-4ec1-b8a0-845652868073
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- Hamming Error Correction Code (ECC)
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- Add extra parity bits to identify the position of the single-bit error, and the word with parity bits has a Hamming distance of 3.
- For 8-bit data word, we need 4 parity bits, respectively placed at the 1,2,4,8th bit of the 12-bit code.
- For larger words, the number of parity bits can be calculated as $p \ge \log_2(p+d+1)$
- See FIGURE 5.24 for detail
hl-page:: 500
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- Single error correction and Double error detection
hl-page:: 501
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- Make the code's hamming distance 4, by adding a parity bit for the whole code word.
- Also, see the textbook for detail
-
- ## Virtual Machines
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hl-page:: 503
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- System Virtual Machines: run the same ISA as the native hardware
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- A single computer, running multiple VMs, supporting multiple OSs and they share the hardware
- virtual machine monitor (VMM) or hypervisor
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- host and guest
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- protection, managing software, managing hardware
- The cost of processor virtualization depends on the workload.
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- User-level processor-bound programs have 0 virtualization overhead, native speed
hl-page:: 504
ls-type:: annotation
id:: 644f5287-cac6-46c8-ad60-8cee1ca0c57c
hl-color:: yellow
- I/O-intensive workloads, also OS-intensive, have high virtualization overhead. As many system calls and privileged instructions.
hl-page:: 504
ls-type:: annotation
id:: 644f52a8-98fb-466b-92cf-7c0f942382b2
hl-color:: yellow
- Requirements of a Virtual Machine Monitor
ls-type:: annotation
hl-page:: 505
hl-color:: yellow
id:: 644f52db-8deb-4e8b-8a11-e59b2bbfbe26
- Guest software should behave on a VM exactly as if it were running on the native hardware,
ls-type:: annotation
hl-page:: 505
hl-color:: yellow
id:: 644f533e-a31c-4916-bb47-2c97eae78310
- Guest software should not be able to change allocation of real system resources directly.
ls-type:: annotation
hl-page:: 505
hl-color:: yellow
id:: 644f5340-0e7e-4ea2-b337-2779d4092da5
- At least two processor modes, system and user.
ls-type:: annotation
hl-page:: 505
hl-color:: yellow
id:: 644f5401-cfe8-439b-af2e-d91bc6dae442
- A privileged subset of instructions that is available only in system mode; all system resources must be controllable only via these instructions.
ls-type:: annotation
hl-page:: 505
hl-color:: yellow
id:: 644f5403-7aab-4e4e-ae71-87aa2d22bbbd
- ## Virtual Memory
ls-type:: annotation
hl-page:: 506
hl-color:: yellow
id:: 644f4178-a1ca-40e3-b488-3ce044954e46
collapsed:: true
- Making Address Translation Fast: the TLB
ls-type:: annotation
hl-page:: 517
hl-color:: yellow
id:: 644f5d06-3450-4d12-96e5-374712790d9e
collapsed:: true
- TLB entry
- Tag holds a portion of the VPN, and data entry holds a PPN.
hl-page:: 517
ls-type:: annotation
id:: 644f5d6e-0c4e-48ad-9284-7b6247cc3d15
hl-color:: yellow
- TLB will need to include other status bits, such as the dirty and the reference bits.
hl-page:: 518
ls-type:: annotation
id:: 644f5d87-be05-4020-a8e8-d23c4a0fcfa4
hl-color:: yellow
- Cache-like considerations
- Write policy: write-back, since the miss rate is low
- Associativity: decided by the number of TLB entries
- Replacement: many systems provide some support for random replacement, because LRU are expensive to implement especially by hardware
hl-page:: 518
ls-type:: annotation
id:: 644f5f4f-8fce-4a04-9ccc-eb988f0e3ed3
hl-color:: yellow
- The Intrinsity FastMATH TLB
ls-type:: annotation
hl-page:: 519
hl-color:: yellow
id:: 644f60f0-680e-4aa0-a0de-165342178045
- 4K page and 32-bit AS lead to 20-bit VPN. Thus 20-bit tag, 20-bit data, and some other bookkeeping bits
- 16-way fully associative TLB, compare VPN against all tags
- On TLB miss, MIPS hardware saves the page number of the reference in a special register and raise exception.
hl-page:: 519
ls-type:: annotation
id:: 644f61e2-eb58-44d5-8b89-b55c3708f25a
hl-color:: yellow
- The hardware maintains an index that indicates the recommended entry to replace, which is chosen randomly.
hl-page:: 519
ls-type:: annotation
id:: 644f62bd-6a29-40bc-a634-15fed6bc1ec9
hl-color:: yellow
- TLB miss routine in OS indexes the table with relevant registers.
- Using a special set of system instructions that can update the TLB, OS handler set replace an entry with the new entry fetched from memory
hl-page:: 519
ls-type:: annotation
id:: 644f6250-82e1-4286-b25a-e4f4eb0eb622
hl-color:: yellow
- A true page fault occurs if the PTE does not have a valid PA
hl-page:: 519
ls-type:: annotation
id:: 644f62a6-7b6d-4434-bc3d-233892af468f
hl-color:: yellow
- Integrating Virtual Memory, TLBs, and Caches
ls-type:: annotation
hl-page:: 519
hl-color:: yellow
id:: 644f6050-cd77-4d32-afdb-3bf8a90302b7
collapsed:: true
- FIGURE 5.31 Processing a read or a write-through in the Intrinsity FastMATH TLB and cache.
ls-type:: annotation
hl-page:: 521
hl-color:: yellow
id:: 644f60d4-72c9-41e9-b976-d1ed1c07d830
- Cache and TLB
- In the simplest case, all memory addresses are translated to PAs before the cache access. This is slow.
hl-page:: 522
ls-type:: annotation
id:: 644f6370-8fd9-4a5e-92e3-09b74f6baa04
hl-color:: yellow
- Virtually addressed cache: uses tags from VAs, VIVT, to avoid using TLB before cache access (unless a TLB miss), which takes TLB out of critical path.
hl-page:: 522
ls-type:: annotation
id:: 644f6397-14d2-491c-9cef-bbfd6e5cca8f
hl-color:: yellow
- Aliasing occurs when the same object has two names. In this case, 2 VAs for the same page. Then one physical page has two copies in cache, introducing consistency issue.
hl-page:: 523
ls-type:: annotation
id:: 644f6434-eb87-405e-9190-4f67466af467
hl-color:: yellow
- Common compromise: virtually indexed but physically tagged, VIPT. Use the page offset portion of the address, which is identical in VA and PA, as the index of cache.
hl-page:: 523
ls-type:: annotation
id:: 644f6491-3e52-4db7-a824-5988e124ee1c
hl-color:: yellow
- Implementing Protection with Virtual Memory (Trivial)
hl-page:: 523
ls-type:: annotation
id:: 644f65cf-03a5-4132-b091-e08b9ce9002a
hl-color:: yellow
collapsed:: true
- Requirement for Hardware
- Support at least 2 priority levels of process
- Provide a portion of the processor state that a user process can read but not write.
ls-type:: annotation
hl-page:: 523
hl-color:: yellow
id:: 644f65f9-38a8-4ead-90f5-494c0b2e3191
- Provide mechanisms whereby the processor can go from user mode to supervisor mode and vice versa. In MIPS, `syscall` and `eret`
hl-page:: 524
ls-type:: annotation
id:: 644f660f-7534-4124-9b7e-32cd2ce2c77a
hl-color:: yellow
- Handling TLB Misses and Page Faults
ls-type:: annotation
hl-page:: 525
hl-color:: yellow
id:: 644f65b8-c079-42ce-a6b6-e1c56dbf45e9
- TLB miss can indicate one of two possibilities: Page in memory and True page fault
hl-page:: 525
ls-type:: annotation
id:: 644f67c6-de09-4546-b3a6-cbb286cca5bb
hl-color:: yellow
- MIPS handles a TLB miss in software. It brings in PTE from memory and then re-executes the instruction that caused the TLB miss. Upon re-executing, it will get a TLB hit.
hl-page:: 525
ls-type:: annotation
id:: 644f6897-2635-4cb9-ae6b-2515dc05694b
hl-color:: yellow
- We must prevent load/store from actually completing when there is an exception, when implementing the pipeline
hl-page:: 526
ls-type:: annotation
id:: 644f68df-1f9b-4430-a2ea-09ee1ca7361f
hl-color:: yellow
- General process of TLB handling
- Upon a TLB miss, the MIPS hardware saves the page number of the reference in `BadVAddr` and generates exception.
hl-page:: 527
ls-type:: annotation
id:: 644f6974-151b-46fa-afe2-ceed4ec48722
hl-color:: yellow
- Control is transferred to address `0x8000_0000`, the location of the TLB miss handler.
hl-page:: 528
ls-type:: annotation
id:: 644f69a6-31f7-4f57-8c78-75a19f0d83fd
hl-color:: yellow
- MIPS hardware places everything you need in the `Context` register: `base of page table | VPN`
hl-page:: 528
ls-type:: annotation
id:: 644f69dd-753d-4df6-b0fc-4f112a12f0ce
hl-color:: yellow
- Since TLB misses are quite frequent, the handler is simple
```asm
TLBmiss:
mfc0 $k1,Context # copy address of PTE into temp $k1
lw $k1,0($k1) # put PTE into temp $k1
mtc0 $k1,EntryLo # put PTE into special register EntryLo
tlbwr # put EntryLo into TLB entry at Random
eret # return from TLB miss exception
```
- TLB miss routine does not check validity of the page, but rather directly loads the PTE into TLB. If it is a true page fault, let the processor generate the Page Fault exception.
- TLB miss routine does not save process state, since it doesn't need to change anything
- TLB miss has a separate handler address, saving the effort to diagnose exception type from `Cause` register
- The process of handling a page fault is laborious. See FIGURE 5.34 for detail.
hl-page:: 530
ls-type:: annotation
id:: 644f6cf2-142f-4b34-a4c1-06de2a87879a
hl-color:: yellow
- To avoid the problem of a page fault during this low-level exception code, MIPS sets aside a portion of its address space that cannot have page faults, called `unmapped`.
hl-page:: 529
ls-type:: annotation
id:: 644f6d39-ad59-4a15-81a9-8dede8bef344
hl-color:: yellow
- Aside: The VMM implements memory control by maintaining a shadow page table. See textbook for detail
hl-page:: 529
ls-type:: annotation
id:: 644f6d8d-7c2f-4cb7-b689-eb282d35f411
hl-color:: yellow
- ## A Common Framework for Memory Hierarchy
ls-type:: annotation
hl-page:: 533
hl-color:: yellow
id:: 644e610b-15ef-47cd-8701-7bf7be87f16c
collapsed:: true
- Question 1: Where Can a Block Be Placed?
ls-type:: annotation
hl-page:: 534
hl-color:: yellow
id:: 644f6e31-ed3f-4bbf-8f30-53fe28e9e518
- This entire range of schemes can be thought of as variations on a set-associative scheme where the number of sets and the number of blocks per set varies
hl-page:: 534
ls-type:: annotation
id:: 644f6e76-bf1e-4def-b9c0-75f1faf3b5c6
hl-color:: yellow
- As cache size grows, the benefit of increasing associativity is slight.
- Question 2: How Is a Block Found?
ls-type:: annotation
hl-page:: 535
hl-color:: yellow
id:: 644f6ec3-e710-4abf-94a2-9f0c362e40e8
- VM uses full associative, while cache/TLB uses set associative
- Question 3: Which Block Should Be Replaced on a Cache Miss?
ls-type:: annotation
hl-page:: 536
hl-color:: yellow
id:: 644f6f0b-c5e3-4c38-90ec-67e3118b5c3d
- For hardware, random or approximated LRU, since they are simple to build
- In virtual memory, some form of LRU is always approximated, in that miss penalty is significant
hl-page:: 536
ls-type:: annotation
id:: 644f6f9a-a898-4b20-88c0-588c940ec793
hl-color:: yellow
- Question 4: What Happens on a Write?
ls-type:: annotation
hl-page:: 536
hl-color:: yellow
id:: 644f6fd5-59c8-41e3-8ede-402475ac6a72
- A summary of pros and cons for Write-back and Write-through
- When write latency is unacceptable, we tend to use Write-back
- The Three Cs: An Intuitive Model for Understanding the Behavior of Memory Hierarchies
ls-type:: annotation
hl-page:: 538
hl-color:: yellow
id:: 644f6ffe-256a-4252-af5b-5a2a8d03fc2e
- Compulsory, Capacity and Conflict misses
- Note that, compulsory misses can be reduced by increasing the block size
- ## Using a Finite-State Machine to Control a Simple Cache
ls-type:: annotation
hl-page:: 540
hl-color:: yellow
id:: 644f418c-dea9-442d-9f38-a60aef123e15
collapsed:: true
- Settings: Direct-mapped, Write-back and write-allocate, 16-Byte block, 16-KB total
- 10-bit Index, 4-bit Offset, 18-bit Tag
- Signals: 2 sets of signals, respectively CPU-Cache and Cache-Memory
- Read/Write, Valid, Address, Read data, Write data, Ready
- FSM for a Simple Cache Controller
ls-type:: annotation
hl-page:: 543
hl-color:: yellow
id:: 644f731a-a08e-4b86-ace7-800cf640accb
- Idle: Waits for a valid CPU request
- Compare Tag
- Test hit or miss: Select block with the index field, and then compare the tag, last check valid.
- If hit, set `CacheReady` and go back to Idle. If write, set the dirty bit; If read, set the `ReadData`
- If miss, set tag of the victim block to required address. Then go to Allocate or Write-back, determined by the dirty bit
- Note that, this state can be split into compare and access, to reduce latency
- Write-back: Writes a block to Memory (and wait for Memory's write ready). On completion, go to Allocate (since we have to wait for new data).
- Allocate: Waits for the Ready signal from Memory. On completion, goes to Compare Tag.
- ## Parallelism and Memory Hierarchy: Cache Coherence
ls-type:: annotation
hl-page:: 545
hl-color:: yellow
id:: 644f41a2-4c7b-4b27-b75e-ea06924fa51e
- **Coherence** defines what values can be returned by a read
hl-page:: 545
ls-type:: annotation
id:: 644f76e2-d5bc-47b0-90dd-c7ff33f07f13
hl-color:: yellow
- A memory system is coherent if:
hl-page:: 545
ls-type:: annotation
id:: 644f77a6-d507-4b1a-bc25-7f42648fd943
hl-color:: yellow
- A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P.
ls-type:: annotation
hl-page:: 545
hl-color:: yellow
id:: 644f77b5-83a5-4fb1-b3a6-3a2db489da39
- A read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses.
ls-type:: annotation
hl-page:: 545
hl-color:: yellow
id:: 644f77c2-e346-4ffc-bb20-a1b3933fe9fc
- Writes to the same location are serialized; that is, two writes to the same location by any two processors are seen in the same order by all processors.
ls-type:: annotation
hl-page:: 546
hl-color:: yellow
id:: 644f77ca-4b61-4296-8a04-a7781102a0a2
- **Consistency** determines when a written value will be returned by a read.
hl-page:: 545
ls-type:: annotation
id:: 644f76e7-a61d-4f42-9c8a-adc7eb920a8c
hl-color:: yellow
- Basic Schemes for Enforcing Coherence
ls-type:: annotation
hl-page:: 546
hl-color:: yellow
id:: 644f7883-18c3-43d5-a7ed-51fac0fb3d83
- Migration: A data item can be moved to a local cache and used there in a transparent fashion.
ls-type:: annotation
hl-page:: 546
hl-color:: yellow
id:: 644f78a3-7065-435c-8ee6-21ae194c1961
- Replication: When shared data are being ==simultaneously read==, the caches make a copy of the data item in the local cache.
ls-type:: annotation
hl-page:: 547
hl-color:: yellow
id:: 644f78b7-c9fa-4854-824d-a8d0952ad3be
- cache coherence protocols, tracking the state of any sharing of a data block
hl-page:: 547
ls-type:: annotation
id:: 644f7956-11ad-4140-b966-6d2061ae6fb2
hl-color:: yellow
- snooping
ls-type:: annotation
hl-page:: 547
hl-color:: yellow
id:: 644f7a3d-783f-49d2-b697-91200284b2c8
- For each block, the caches which have this block, hold both the copy of data and a copy of the sharing status of this block.
- caches are accessible via some broadcast medium
hl-page:: 547
ls-type:: annotation
id:: 644f7ab7-b97c-41a9-8780-e9281ab19565
hl-color:: yellow
- cache controllers monitor (snoop) on the medium, to determine whether they have a copy of a block that is requested on a bus or switch access.
hl-page:: 547
ls-type:: annotation
id:: 644f7ad5-2103-4b23-a6c0-0417d431eb02
hl-color:: yellow
- write invalidate protocol: invalidate copies in other caches on a write. When others want to read/write later, they miss and fetch from memory. When others want to write simultaneously, there is a race and there is always a winner.
hl-page:: 547
ls-type:: annotation
id:: 644f797d-e82e-49fc-97b0-df7034494d5f
hl-color:: yellow
- ensure that a processor has exclusive access to a data item before it writes that item
- Parallelism and the Memory Hierarchy: Redundant Arrays of Inexpensive Disks
hl-page:: 550
ls-type:: annotation
id:: 644f41d0-39d8-476b-8d62-08e2bf5979ef
hl-color:: yellow
collapsed:: true
- Refer to ((6437e8b0-b179-46c1-9173-e9b080273f7e))
- ## Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
ls-type:: annotation
hl-page:: 557
hl-color:: yellow
id:: 644e0503-5ee5-4da8-bf62-04b2fa91e5f9
collapsed:: true
- To support multiple issue (fetch more instructions per cycle), a popular technique is to break the cache into banks and allow multiple, independent, parallel accesses (if the addresses are in different banks).
hl-page:: 558
ls-type:: annotation
id:: 644fae8b-080a-4bed-8e02-08519a34b547
hl-color:: yellow
- nonblocking cache: *Hit under miss* allows additional cache hits during a miss, while *miss under miss* allows multiple outstanding cache misses.
hl-page:: 558
ls-type:: annotation
id:: 644faeff-a7cf-4a48-b257-50e090ca62be
hl-color:: yellow
- Core i7 has prefetch mechanism for data accesses
hl-page:: 559
ls-type:: annotation
id:: 644faf31-abe7-4938-b43a-15ca77c5a20a
hl-color:: yellow
- Going Faster: Cache Blocking and Matrix Multiply
ls-type:: annotation
hl-page:: 561
@ -2190,25 +2676,59 @@ file-path:: ../../../../assets/Computer_Organization_and_Design_1681729306797_0.
hl-page:: 564
hl-color:: yellow
id:: 644deab8-5929-424b-a0bb-9944268d757e
- Word List 5
collapsed:: true
- rug
- Pitfall: Having less set associativity for a shared cache than the number of cores or threads sharing that cache.
ls-type:: annotation
hl-page:: 565
hl-color:: yellow
id:: 644fb0df-1bf0-479c-bb16-de1b6729faa4
- Word List 5
- rug 小块地毯
hl-page:: 462
hl-color:: green
ls-type:: annotation
id:: 644dded8-ffe3-4d2e-abbe-d4374b5b30af
- proximity
hl-color:: green
- proximity (时间或空间)接近,邻近,靠近:
ls-type:: annotation
hl-page:: 478
hl-color:: green
id:: 644e0631-3612-4778-86c2-e6f062b426ab
- incur
ls-type:: annotation
- incur 招致，引发；蒙受
hl-page:: 489
hl-color:: green
id:: 644e59e3-12be-418f-bd07-bb228ec2a8ac
- ## Dependable Memory Hierarchy
ls-type:: annotation
hl-page:: 497
id:: 644e59e3-12be-418f-bd07-bb228ec2a8ac
hl-color:: green
- Voila 〈法〉那就是,瞧(表示事情成功或满意之感叹词用语)
hl-page:: 501
ls-type:: annotation
id:: 644f4c11-76c4-4c50-8278-f5a18415cad6
hl-color:: green
- culprit 罪犯；肇事者
hl-page:: 505
ls-type:: annotation
id:: 644f5381-dd30-4674-b37e-ce080e71a4a2
hl-color:: green
- duality 二元性；
hl-page:: 515
ls-type:: annotation
id:: 644f5b71-6ca0-47f3-8a20-9cc15c1fa0e0
hl-color:: green
- simplistic 过分简单化的
hl-page:: 545
ls-type:: annotation
id:: 644f7695-12e8-4ffe-a6c7-105b596300de
hl-color:: green
- saga 冒险故事；传说；英雄事迹
ls-type:: annotation
hl-page:: 561
hl-color:: green
id:: 644fafd9-52b6-4378-b808-35d07dd67108
- underscore 下画线
hl-page:: 568
ls-type:: annotation
id:: 644fb0c3-4e0b-41ea-8edb-01e11b936c65
hl-color:: green
- # Parallel Processors from Client to Cloud
ls-type:: annotation
hl-page:: 586
hl-color:: yellow
id:: 644dea78-9ad9-4322-a05d-1b30789b85a8
id:: 644fb152-58ba-4049-b461-37264438cfde

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@ -14,3 +14,114 @@ file-path:: ../assets/HTMFS_Strong_Consistency_Comes_for_Free_with_1682647018871
- Earlier FSs optimize for performance, but provide loose consistency guarantees
- With the speedup of modern storage devices, strong consistency can ease the pain of software programming.
- Strong consistency implies per-request sequential consistency.
- atomic modification: inode level locks
- Transaction semantics after crash recovery, all-or-none
- modern storage devices, PMEM, or non-volatile RAM
hl-page:: 2
ls-type:: annotation
id:: 64511829-234d-45a3-9d1c-f50d60466704
hl-color:: yellow
- Problem with existent PM FS: complicated mechanism, write amplification
- Previous approaches are limited to atomicity unit of CPU writes.
ls-type:: annotation
hl-page:: 2
hl-color:: yellow
id:: 64511979-cee9-4f46-87ba-6bbfe86bf0a4
- Problem with RTM: Block IO abort RTM; PM can be accessed as RAM, but with cache involved, also abort RTM
- enhanced asynchronous DRAM refresh (eADR)
hl-page:: 3
ls-type:: annotation
id:: 64511f4c-4338-41ad-9264-263ed5a08bf4
hl-color:: yellow
- guarantee the persistence of memory writes once they become globally visible,
ls-type:: annotation
hl-page:: 3
hl-color:: yellow
id:: 6451204b-d1b8-46ed-8ec9-3a7c2d05244e
- eliminate the need for cache flush to sync with PM
- See [Detail](https://www.intel.com/content/www/us/en/developer/articles/technical/eadr-new-opportunities-for-persistent-memory-applications.html)
- Several challenges with RTM-PM
hl-page:: 3
ls-type:: annotation
id:: 6451205e-7f48-43e8-8704-d221d806cc18
hl-color:: yellow
- RTM is small, while FS data transfer are generally large
- Some FS operations have long code-path, lengthening RTM section, increasing conflict abort rate
- Hardware-assisted Optimistic Persistence
ls-type:: annotation
hl-page:: 3
hl-color:: yellow
id:: 64512109-8ab0-49aa-b6a3-1524df0631ef
- eADR, HTM with cooperative locks as fallback
- HTMFS, a user-space PM file systems base on ZoFS
ls-type:: annotation
hl-page:: 3
hl-color:: yellow
id:: 64512150-84a0-4839-aef6-48bb872fa776
- Background and Motivation
ls-type:: annotation
hl-page:: 3
hl-color:: yellow
id:: 6451215b-a495-4d6f-9427-f5c0c6685a28
- Persistent Memory and PM File Systems
ls-type:: annotation
hl-page:: 4
hl-color:: yellow
id:: 645124e7-37ae-404c-bc83-2ae78628767f
- 主要的点就是，PM 是 ==byte-addressable==
- Existing PMFS: The only difference would be leveraging atomic instructions to provide small updates up to a single cache line
hl-page:: 4
ls-type:: annotation
id:: 64526ec1-37e2-4891-bba8-eeb07c6e02d3
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- 作者认为现有的PMFS没啥创新，在一致性上还是用的旧东西，除了用 PM 提供的 atomic inst 来简化某些原子操作
- 2.3 Hardware Transactional Memory
ls-type:: annotation
hl-page:: 4
hl-color:: yellow
id:: 6452709d-6036-4dcd-8821-c106562565fe
- RTM的基本用法：把 critical section 用 `xbegin` 和 `xend` 包起来
hl-page:: 4
ls-type:: annotation
id:: 645270e0-2153-4414-8b22-762cfc113c19
hl-color:: yellow
- Conflict aborts
hl-page:: 4
ls-type:: annotation
id:: 64527149-e50e-46c8-990f-0465060f9a5a
hl-color:: yellow
- 硬件维护trx的 read set 和 write set，如果在提交之前，有别的 core 读 write set 或者写 read set，就会 abort。这些东西都在 cache 里面，维护这些也是用 cache coherence protocol
- Capacity aborts.
ls-type:: annotation
hl-page:: 4
hl-color:: yellow
id:: 645271fa-ff04-4263-a2f2-d1879c1fb857
- 受到每个core本地cache比如L1，的大小的限制
- Other aborts
hl-page:: 4
ls-type:: annotation
id:: 64527248-77dc-4d32-8a2b-737b7329d2e9
hl-color:: yellow
- 不兼容指令，中断（所以打IO显然不行）等东西
- 2.4 HTM in PM File Systems
ls-type:: annotation
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- HTM的操作是在 cache 里面的，没有持久化保证，除非显式刷到内存/PM里。但是 临界区内不能刷（刷了就abort），临界区之后要是被切走就寄了（除非上锁，不如直接上锁）
- Intel 的新东西表示，它可以做到commit到cache里面就能持久化
- 3 Design
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- 直接把 FS 操作用HTM包起来不现实，因为FS的操作都很长很大
- 3.1 HOP
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- 非常自然的想法：把一个操作，或者说trx，拆成小的
- 三种操作分类：
- Read、Invisible write(内部的东西，比如块分配信息) 、Visible write(应用程序可见的)
- 只有 Visible Write 用 HTM 实现，Invisible 和 Read 通过别的机制来实现

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- RAID Interface
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- Look like a ==big, fast and reliable disk==, which provides an abstraction of ==a linear array of blocks==. Usually, a RAID is connected to the host through ==standard interfaces== (e.g. SATA)
- Internally, the RAID controller decides how to perform ==physical I/Os== in order to complete a single ==logical I/O==.
- At a high level, a RAID is very much a specialized computer system: it has a processor, memory, and disks; however, instead of running applications, it runs specialized software designed to operate the RAID.